Datasheet

ADV3200/ADV3201
Rev. 0 | Page 12 of 36
I/O SCHEMATICS
OUT
VREF
07176-054
4kΩ
(ADV3201 ONLY)
Figure 7. Enabled Output
(See Also Figure 16)
3.7pF
4kΩ
(ADV3201 ONLY)
VREF
OUT
07176-055
Figure 8. Disabled Output
(See Also Figure 16)
VNEG
IN
07176-056
Figure 9. Receiver
(See Also Figure 16)
VNEG
IN
5µA
07176-058
Figure 10. Receiver with Sync-Tip Clamp Enabled
(See Also Figure 16)
RESET
DGND
DVCC
1kΩ
25kΩ
07176-057
Figure 11. Reset Input
(See Also Figure 16)
DGND
1kΩ
07176-059
DGND
25kΩ
(CS ONLY)
CLK, UPDATE,
DATA IN,
OSDS, CS
Figure 12. Logic Input
(See Also Figure 16)
DVCC
DGND
DATA OUT
07176-060
Figure 13. Logic Output
(See Also Figure 16)
VNEG
VREF
VCLAMP
07176-061
50µA
6kΩ
Figure 14. VCLAMP Input
(See Also Figure 16)
VNEG
VPOS
VPO
S
VREF
07176-062
2.5kΩ
(5kΩ FOR ADV3201)
2.5kΩ
(5kΩ FOR ADV3201)
Figure 15. VREF Input
(See Also Figure 16)
VPOS
VNEG
VREF, VCLAMP,
OSD, IN, OUT
DVCC
DGND
CLK, RESET,
UPDATE, CS,
DATA IN,
DATA OUT,
OSDS
07176-063
Figure 16. ESD Protection Map