Datasheet

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HDMI/DVI TMDS Equalizer

ADV3003

Rev. 0

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FEATURES

One input, one output HDMI/DVI high speed signal

equalizer/driver

Enables HDMI 1.3 receive-compliant input

Four TMDS channels per input/output

Supports 250 Mbps to 2.25 Gbps data rates

Supports 25 MHz to 225 MHz pixel clocks

Fully buffered unidirectional inputs/outputs

Equalized inputs for operation with long HDMI cables

(20 meters at 2.25 Gbps)

Pre-emphasized outputs

Matched 50 Ω input and output on-chip terminations

Low added jitter

Transmitter disable feature

Reduces power dissipation

Disables input terminations

Single-supply operation (3.3 V)

Standards compliant: HDMI receiver, DVI

40-lead, 6 mm × 6 mm, RoHS-compliant LFCSP

APPLICATIONS

Multiple input displays

Advanced television set (HDTV) front panel connectors

HDMI/DVI cable extenders

FUNCTIONAL BLOCK DIAGRAM

IP[3:0]

IN[3:0]

VTTI

OP[3:0]

AVEE

VTTO

AVCC

ON[3:0]

–

BUFFER

CONTROL

LOGIC

HIGH SPEED BUFFERED

PE_EN TX_EN

PARALLEL

CONTROL

ADV3003

7212-001

Figure 1.

TYPICAL APPLICATION DIAGRAM

MEDIA CENTER

SET-TOP BOX

DVD PLAYER

HDTV SET

4:1 HDMI

SWITCH

ADV3003

HDMI

RECEIVER

FRONT PANEL

CONNECTOR

BACK PANEL

CONNECTORS

GAME

CONSOLE

07212-002

Figure 2.

GENERAL DESCRIPTION

The ADV3003 is a 4-channel transition minimized differential

signaling (TMDS) buffer featuring equalized inputs and

pre-emphasized outputs. The ADV3003 features 50 Ω input

and output terminations, providing full-swing output signal

recovery and minimizing reflections for improved system

signal integrity. The ADV3003 is targeted at HDMI™/DVI

applications and is ideal for use in systems with long cable

runs, long PCB traces, and designs with interior cabling.

The ADV3003 is provided in a 40-lead, LFCSP, surface-mount,

RoHS-compliant, plastic package and is specified to operate

over the −40°C to +85°C temperature range.

PRODUCT HIGHLIGHTS

1. Supports data rates up to 2.25 Gbps, enabling 1080p deep

color (12-bit color) HDMI formats and greater than UXGA

(1600 × 1200) DVI resolutions.

2. The 12 dB input cable equalizer enables the use of long

cables at the input. For a typical 24 AWG cable, the

ADV3003 compensates for more than 20 meters at data

rates up to 2.25 Gbps.

3. The selectable 6 dB of output pre-emphasis allows the

ADV3003 to drive high loss output cables or long PCB traces.

4. Matched 50 Ω on-chip input and output terminations

improve system signal integrity.

5. An external control pin, PE_EN, sets the output

pre-emphasis to either 0 dB or 6 dB.

6. An external control pin, TX_EN, simultaneously disables

both the transmitter and the on-chip input terminations.

This feature reduces the power dissipation of the ADV3003

and indicates to a connected source when the ADV3003 is

disabled.

Summary of content (16 pages)

PAGE 1
HDMI/DVI TMDS Equalizer ADV3003 FEATURES FUNCTIONAL BLOCK DIAGRAM PE_EN TX_EN PARALLEL CONTROL VTTI IP[3:0] IN[3:0] AVEE CONTROL LOGIC + 4 – 4 EQ BUFFER HIGH SPEED VTTO PE 4 + 4 – OP[3:0] ON[3:0] BUFFERED Figure 1.
PAGE 2
ADV3003 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 10 Functional Block Diagram ..............................................................
PAGE 3
ADV3003 SPECIFICATIONS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. Table 1.
PAGE 4
ADV3003 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter AVCC to AVEE VTTI VTTO Internal Power Dissipation High Speed Input Voltage High Speed Differential Input Voltage Parallel Interface (TX_EN, PE_EN) Storage Temperature Range Operating Temperature Range Junction Temperature Rating 3.7 V AVCC + 0.6 V AVCC + 0.6 V 2.0 W AVCC − 1.4 V < VIN < AVCC + 0.6 V 2.0 V AVEE − 0.3 V < VIN < AVCC + 0.
PAGE 5
ADV3003 40 39 38 37 36 35 34 33 32 31 NC NC NC AVEE NC NC NC NC AVCC NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADV3003 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 AVCC PE_EN TX_EN AVEE AVCC AVCC AVEE AVCC AVCC NC NOTES 1. NC = NO CONNECT. 2. THE ADV3003 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE, WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE TO MEET ELECTRICAL AND THERMAL SPECIFICATIONS.
PAGE 6
ADV3003 TYPICAL PERFORMANCE CHARACTERISTICS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. HDMI CABLE ADV3003 DIGITAL PATTERN GENERATOR SERIAL DATA ANALYZER EVALUATION BOARD REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07212-004 SMA COAX CABLE 0.125UI/DIV AT 2.25Gbps 0.125UI/DIV AT 2.25Gbps 07212-008 0.
PAGE 7
ADV3003 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. HDMI CABLE ADV3003 DIGITAL PATTERN GENERATOR SERIAL DATA ANALYZER EVALUATION BOARD REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07212-009 SMA COAX CABLE 0.125UI/DIV AT 2.25Gbps 0.125UI/DIV AT 2.25Gbps 07212-013 0.125UI/DIV AT 2.25Gbps Figure 11.
PAGE 8
ADV3003 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. 0.6 0.6 ALL CABLES = 24 AWG PE = 6dB 0.5 0.5 0.4 0.4 JITTER (UI) JITTER (UI) ALL CABLES = 24 AWG 1080p, 12- BIT 0.3 1.65Gbps 0.2 0.3 1080p, 12-BIT 0.2 1080p, 8-BIT 720p/1080i, 8-BIT 1080p, 8-BIT 1.65Gbps 0.
PAGE 9
ADV3003 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. 80 50 45 70 40 60 JITTER (ps) JITTER (ps) 35 50 40 DJ p-p 30 DJ p-p 30 25 20 15 20 10 5 RJ rms RJ rms 0 0.5 1.0 1.5 2.0 DIFFERENTIAL INPUT VOLTAGE SWING (V) 0 2.5 07212-020 0 2.9 3.1 3.3 3.5 3.7 INPUT COMMON-MODE VOLTAGE (V) Figure 20.
PAGE 10
ADV3003 THEORY OF OPERATION INTRODUCTION The primary function of the ADV3003 is to buffer the four high speed channels of a single HDMI or DVI link. The HDMI/DVI link consists of four differential, high speed channels and four auxiliary single-ended, low speed control signals. The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× the data-word clock frequency for data rates up to 2.25 Gbps.
PAGE 11
ADV3003 The ADV3003 has an external control pin, TX_EN. The TX_EN pin must be connected to either a logic high (1) or low (0), in accordance with the logic values set forth in Table 1. The use of the TX_EN pin is described in Table 5. When the transmitter is enabled by setting TX_EN to 1, both the input and output terminations are enabled. Setting TX_EN to 0 disables the transmitter, reducing power when the transmitter is not in use.
PAGE 12
ADV3003 APPLICATION NOTES The ADV3003 is a TMDS buffer featuring equalized inputs and pre-emphasized outputs. It is intended for use as a buffer in HDMI/DVI systems with long input cable runs, and is fully HDMI 1.3 receive-compliant. PINOUT The ADV3003 is designed to have an HDMI/DVI receiver pinout at its input and a transmitter pinout at its output.
PAGE 13
ADV3003 Layout for the TMDS Signals The TMDS differential pairs can either be microstrip traces, routed on the outer layer of a board, or stripline traces, routed on an internal layer of the board. If microstrip traces are used, there should be a continuous reference plane on the PCB layer directly below the traces. If stripline traces are used, they must be sandwiched between two continuous reference planes in the PCB stack-up.
PAGE 14
ADV3003 TMDS Terminations The ADV3003 provides internal 50 Ω single-ended terminations for all its high speed inputs and outputs. The output termination resistors are always enabled and act to back-terminate the output TMDS transmission lines. These back-terminations act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed.
PAGE 15
ADV3003 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.30 12° MAX 40 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOT TOM VIEW) 21 20 10 11 0.25 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.