Datasheet

ADuM3160 Data Sheet
Rev. C | Page 8 of 16
Table 10. Truth Table, Control Signals, and Power (Positive Logic)
V
SPU
Input
1
V
UD+
, V
UD−
State
1
V
BUS1
, V
DD1
State
V
BUS2
, V
DD2
State
V
DD+
, V
DD−
State
1
V
PIN
Input
1
V
SPD
Input
1
Description
High Active Powered Powered Active High High
Input and output logic set for full speed logic
convention and timing.
Low
Active
Powered
Powered
Active
High
Low
Input and output logic set for low speed logic
convention and timing.
Low Active Powered Powered Active High High
Not allowed. V
SPU
and V
SPD
must be set to the same
value. The USB host detects a communication error.
High Active Powered Powered Active High Low
Not allowed. V
SPU
and V
SPD
must be set to the same
value. The USB host detects a communication error.
X Z Powered Powered Z Low X
Upstream Side 1 presents a disconnected state to
the USB cable.
X X Unpowered Powered Z X X
When power is not present on V
DD1
, the down-
stream data output drivers revert to the high-Z
state within 32 bit times. The downstream side
initializes in the high-Z state.
X Z Powered Unpowered X X X
When power is not present on V
DD2
, the upstream
side disconnects the pull-up and disables the
upstream drivers within 32 bit times.
1
X is don’t care; Z is the high impedance output state.
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