Datasheet

Data Sheet ADuM3160
Rev. C | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.5 V ≤ V
BUS1
≤ 5.5 V, 4.5 V ≤ V
BUS2
≤ 5.5 V; 3.1 V ≤ V
DD1
≤ 3.6 V, 3.1 V ≤ V
DD2
≤ 3.6 V. All minimum/maximum specifications apply over
the entire recommended operation range, unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.3 V. All
voltages are relative to their respective grounds.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
1
DC SPECIFICATIONS
Total Supply Current
2
1.5 Mbps 750 kHz logic signal rate, C
L
= 450 pF
V
DD1
or V
BUS1
Supply Current I
DD1 (L)
5 7 mA
V
DD2
or V
BUS2
Supply Current I
DD2 (L)
5 7 mA
12 Mbps 6 MHz logic signal rate, C
L
= 50 pF
V
DD1
or V
BUS1
Supply Current I
DD1 (F)
6 8 mA
V
DD2
or V
BUS2
Supply Current
I
DD2 (F)
6
8
mA
Idle Current
V
DD1
or V
BUS1
Idle Current I
DD1 (I)
1.7 2.3 mA
Input Currents
I
DD−
, I
DD+
,
I
UD+
, I
UD−
,
I
SPD
, I
PIN
,
I
SPU
, I
PDEN
−1 +0.1 +1 µA
0 V ≤ V
DD−
, V
DD+
, V
UD+
, V
UD−
, V
SPD
, V
PIN
,
V
SPU
, V
PDEN
≤ 3.0 V
Single-Ended Logic High Input Threshold V
IH
2.0 V
Single-Ended Logic Low Input Threshold V
IL
0.8 V
Single-Ended Input Hysteresis V
HST
0.4 V
Differential Input Sensitivity V
DI
0.2 V |V
XD+
− V
XD−
|
Logic High Output Voltages
V
OH
2.8
3.6
V
R
L
= 15 kΩ, V
L
= 0 V
Logic Low Output Voltages V
OL
0 0.3 V R
L
= 1.5 kΩ, V
L
= 3.6 V
V
DD1
and V
DD2
Supply Undervoltage Lockout V
UVLO
2.4 3.1 V
V
BUS1
Supply Undervoltage Lockout V
UVLOB1
3.5 4.35 V
V
BUS2
Supply Undervoltage Lockout V
UVLOB2
3.5 4.4 V
Transceiver Capacitance C
IN
10 pF UD+, UD−, DD+, DD− to ground
Capacitance Matching 10 %
Full Speed Driver Impedance Z
OUTH
4 20 Ω
Impedance Matching 10 %
SWITCHING SPECIFICATIONS, I/O PINS,
LOW SPEED
Low Speed Data Rate 1.5 Mbps C
L
= 50 pF
Propagation Delay
3
t
PHL
, t
PLH
325 ns
C
L
= 50 pF, SPD = SPU = low,
V
DD1
, V
DD2
= 3.3 V
Side 1 Output Rise/Fall Time (10% to 90%),
Low Speed
t
RL
, t
FL
75
300
ns
C
L
= 450 pF, SPD = SPU = low,
V
DD1
, V
DD2
= 3.3 V
Low Speed Differential Jitter, Next Transition |t
LJN
| 45 ns C
L
= 50 pF
Low Speed Differential Jitter, Paired Transition |t
LJP
| 15 ns C
L
= 50 pF
SWITCHING SPECIFICATIONS, I/O PINS,
FULL SPEED
Maximum Data Rate 12 Mbps C
L
= 50 pF
Propagation Delay
3
t
PHL
, t
PLH
20 60 70 ns
C
L
= 50 pF, SPD = SPU = high,
V
DD1
, V
DD2
= 3.3 V
Output Rise/Fall Time (10% to 90%), Full Speed t
RF
, t
FF
4 20 ns
C
L
= 50 pF, SPD = SPU = high,
V
DD1
, V
DD2
= 3.3 V
Full Speed Differential Jitter, Next Transition |t
HJN
| 3 ns C
L
= 50 pF
Full Speed Differential Jitter, Paired Transition |t
HJP
| 1 ns C
L
= 50 pF
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