Datasheet

ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
Rev. E | Page 20 of 25
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at both input and output supply pins:
V
DD1
and V
DD2
(see Figure 29). Choose a capacitor value between
0.01 µF a nd 0.1 µF. The total lead length between both ends of the
capacitor and the input power supply pin must not exceed 20 mm.
Using proper PCB design choices, the ADuM1440/ADuM1441/
ADuM1442/ADuM1445/ADuM1446/ADuM1447 readily meets
CISPR 22 Class A (and FCC Class A) emissions standards, as
well as the more stringent CISPR 22 Class B (and FCC Class B)
standards in an unshielded environment. Refer to the AN-1109
Application Note, Recommendations for Control of Radiated
Emissions with iCoupler Devices, for PCB-related EMI mitigation
techniques, including board layout and stack-up issues.
V
DD1
GND
1
V
IA
V
IB
V
IC/
V
OC
V
ID/
V
OD
EN
1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC/
V
IC
V
OD/
V
ID
EN
2
GND
2
11845-018
Figure 29. Recommended Printed Circuit Board Layout, QSOP
V
DD1
GND
1
V
IA
V
IB
V
IC/
V
OC
V
ID/
V
OD
NC/CTRL
1
EN
1
NC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC/
V
IC
V
OD/
V
ID
CTRL
2
NC/EN
2
NC
GND
2
11845-126
Figure 30. Recommended Printed Circuit Board Layout, SSOP
For applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, design the board layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage.
PROPAGATION DELAY-RELATED PARAMETERS
These products are optimized for minimum power consumption
by eliminating as many internal bias currents as possible. As a
result, the timing characteristics are more sensitive to operating
voltage and temperature than in standard iCoupler products.
Refer to Figure 21 through Figure 28 for the expected variation
of these parameters.
Propagation delay is a parameter defined as the time it takes a
logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition can
differ from the propagation delay time of a low-to-high transition.
I
N
PU
T
(V
Ix
)
OUTPUT (V
Ox
)
t
PL
H
t
P
HL
50%
50%
11845-019
Figure 31. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching is the maximum amount of time
the propagation delay differs between channels within a single
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 component.
Propagation delay skew is the maximum amount of time the
propagation delay differs between multiple ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
components operating under the same conditions.
In edge-based systems, it is critical to reject pulses that are too
short to be handled by the encode and decode circuits. The
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 implement a glitch filter to reject pulses less than
the glitch filter operating threshold. This threshold depends on
the operating voltage, as shown in Figure 26. Any pulse shorter
than the glitch filter does not pass to the output. When the refresh
circuit is enabled, pulses that match the glitch filter width have a
small probability of being stretched until corrected by the next
refresh cycle, or by the next valid data through that channel. To
avoid issues with pulse stretching, observe the minimum pulse
width requirements listed in the switching specifications.
DC CORRECTNESS
Standard Operating Mode
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. When
refresh and watchdog functions are enabled by pulling EN
1
and
EN
2
low, in the absence of logic transitions at the input for more
than ~140 µs, a periodic set of refresh pulses indicative of the
correct input state is sent to ensure dc correctness at the output. If
the decoder receives no internal pulses of more than approximately
200 µs, the input side is assumed unpowered or nonfunctional,
in which case, the isolator watchdog circuit forces the output to
a default state. The default state is either high as in the ADuM1440,
ADuM1441, and ADuM1442 versions, or low as in the ADuM1445,
ADuM1446, and ADuM1447 versions.