Datasheet

Data Sheet ADuM1310/ADuM1311
Rev. K | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V. All voltages are relative to their respective grounds.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
ADuM1310, Total Supply Current,
Three Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
2.4 3.2 mA
DC to 1 MHz logic signal
frequency
V
DD2
Supply Current I
DD2 (Q)
1.2 1.6 mA
DC to 1 MHz logic signal
frequency
10 Mbps (BRWZ Grade Only)
V
DD1
Supply Current I
DD1 (10)
6.6 9.0 mA 5 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (10)
2.1 3.0 mA 5 MHz logic signal frequency
ADuM1311, Total Supply Current,
Three Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
2.2 2.8 mA
DC to 1 MHz logic signal
frequency
V
DD2
Supply Current I
DD2 (Q)
1.8 2.4 mA
DC to 1 MHz logic signal
frequency
10 Mbps (BRWZ Grade Only)
V
DD1
Supply Current
I
DD1 (10)
4.5
5.7
mA
5 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (10)
3.5 4.3 mA 5 MHz logic signal frequency
For All Models
Input Currents
I
IA
, I
IB
, I
IC
, I
CTRL1
,
I
CTRL2
, I
DISABLE
−10 +0.01 +10 µA
0 V ≤ V
IA
, V
IB
, V
IC
≤ V
DD1
or V
DD2
,
0 V ≤ V
CTRL1
, V
CTRL2
≤ V
DD1
or V
DD2
,
0 V ≤ V
DISABLE
≤ V
DD1
Logic High Input Threshold V
IH
2.0 V
Logic Low Input Threshold V
IL
0.8 V
Logic High Output Voltages V
OAH
, V
OBH
, V
OCH
(V
DD1
or V
DD2
) − 0.1 5.0 V I
Ox
= −20 µA, V
Ix
= V
IxH
(V
DD1
or V
DD2
) − 0.4 4.8 V I
Ox
= −4 mA, V
Ix
= V
IxH
Logic Low Output Voltages V
OAL
, V
OBL
, V
OCL
0.0 0.1 V I
Ox
= 20 µA, V
Ix
= V
IxL
0.2 0.4 V I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM131xARWZ
Minimum Pulse Width
2
PW 1000 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
1 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 100 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 40 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
50 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
6
t
PSKCD/OD
50 ns C
L
= 15 pF, CMOS signal levels
ADuM131xBRWZ
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 30 50 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 5 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
30 ns C
L
= 15 pF, CMOS signal levels
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