Datasheet

ADuM1100 Data Sheet
Rev. K | Page 16 of 20
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM1100 digital isolator requires no external interface
circuitry for the logic interfaces. A bypass capacitor is recom-
mended at the input and output supply pins. The input bypass
capacitor can conveniently be connected between Pin 3 and
Pin 4 (see Figure 13). Alternatively, the bypass capacitor can be
located between Pin 1 and Pin 4. The output bypass capacitor
can be connected between Pin 7 and Pin 8 or Pin 5 and Pin 8.
The capacitor value should be between 0.01 μF and 0.1 μF. The
total lead length between both ends of the capacitor and the
power supply pins should not exceed 20 mm.
V
DD1
V
I
(DATA IN)
GND
1
V
DD2
V
O
(DATA OUT)
GND
2
(OPTIONAL)
02462-013
Figure 13. Recommended Printed Circuit Board Layout
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay time describes the length of time it takes for
a logic signal to propagate through a component. Propagation
delay time to logic low output and propagation delay time to
logic high output refer to the duration between an input
signal transition and the respective output signal transition
(see Figure 14).
INPUT (V
I
)
OUTPUT (V
O
)
t
PLH
t
PHL
50%
50%
02462-014
Figure 14. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
t
PLH
and t
PHL
and provides an indication of how accurately the
input signal’s timing is preserved in the component’s output
signal. Propagation delay skew is the difference between the
minimum and maximum propagation delay values among
multiple ADuM1100 components operated at the same
operating temperature and having the same output load.
Depending on the input signal rise/fall time, the measured
propagation delay based on the input 50% level can vary from
the true propagation delay of the component (as measured from
its input switching threshold). This is because the input threshold,
as is the case with commonly used optocouplers, is at a different
voltage level than the 50% point of typical input signals. This
propagation delay difference is given by
Δ
LH
= t′
PLH
− t
PLH
= (t
R
/0.8 V
I
)(0.5 V
I
− V
ITH (L-H)
)
Δ
HL
= t′
PHL
− t
PHL
= (t
F
/0.8 V
I
)(0.5 V
I
− V
ITH (H-L)
)
where:
t
PLH
and t
PHL
are the propagation delays as measured from the
input 50% level.
t’
PLH
and t’
PHL
are the propagation delays as measured from the
input switching thresholds.
t
R
and t
F
are the input 10% to 90% rise/fall times.
V
I
is the amplitude of the input signal (0 V to V
I
levels assumed).
V
ITH (L–H)
and V
ITH (H–L)
are the input switching thresholds.
∆
LH
V
ITH(H–L)
INPUT (V
I
)
V
ITH(L–H)
V
I
∆
HL
t
PHL
t'
PHL
t
PLH
t'
PLH
OUTPUT (V
O
)
50%
50%
02462-015
Figure 15. Impact of Input Rise/Fall Time on Propagation Delay