Datasheet

ADuCM360/ADuCM361 Data Sheet
Rev. B | Page 8 of 24
Parameter Test Conditions/Comments Min Typ Max Unit
DAC CHANNEL SPECIFICATIONS R
L
= 5 kΩ, C
L
= 100 pF
Voltage Range Internal reference 0 V
REF
V
External reference 0 1.8 V
DC Specifications
11
Resolution
12
Bits
Relative Accuracy ±3 LSB
Differential Nonlinearity Guaranteed monotonic ±0.5 ±1 LSB
Offset Error 1.2 V internal reference ±2 ±10 mV
Gain Error V
REF
range (reference = 1.2 V) ±0.5 %
NPN Mode
1
Resolution
12
Bits
Relative Accuracy ±3 LSB
Differential Nonlinearity ±0.5 LSB
Offset Error ±0.35 mA
Gain Error ±0.75 mA
Output Current Range 0.008 23.6 mA
Interpolation Mode
1
Only monotonic to 14 bits
Resolution 14 Bits
Relative Accuracy For 14-bit resolution ±4 LSB
Differential Nonlinearity Monotonic (14 bits) ±0.5 LSB
Offset Error 1.2 V internal reference ±2 mV
Gain Error
V
REF
range (reference = 1.2 V)
±1
%
AVDD range ±1 %
DAC AC CHARACTERISTICS
1
Voltage Output Settling Time
10
µs
Digital-to-Analog Glitch Energy
1 LSB change at major carry (maximum
number of bits changes simultaneously
in the DAC0DAT register)
±20 nV-sec
POWER-ON RESET (POR)
POR Trip Level Voltage at DVDD pin
Power-on level 1.6 V
Power-down level 1.6 V
Timeout from POR
1
50 ms
WATCHDOG TIMER (WDT)
1
Timeout Period 0.00003 8192 sec
Timeout Step Size
T3CON[3:2] = 10
7.8125
ms
FLASH/EE MEMORY
1
Endurance
12
10,000 Cycles
Data Retention
13
T
J
= 85°C
10
Years
DIGITAL INPUTS All digital inputs
Input Leakage Current
Digital inputs except for the
RESET,
SWCLK, and SWDIO pins
Logic 1 V
INH
= IOVDD or V
INH
= 1.8 V 140 μA
Internal pull-up disabled 1 nA
Logic 0 V
INL
= 0 V 160 μA
Internal pull-up disabled 10 nA
Input Leakage Current
RESET, SWCLK, and SWDIO pins
Logic 1 140 μA
Logic 0 160 μA
Input Capacitance
1
10 pF
Logic Inputs
Input Low Voltage, V
INL
0.2 × IOVDD V
Input High Voltage, V
INH
0.7 × IOVDD
V