Datasheet

ADuCM360/ADuCM361 Data Sheet
Rev. B | Page 22 of 24
TYPICAL SYSTEM CONFIGURATION
Figure 15 shows a typical ADuCM360/ADuCM361 configuration. This figure illustrates some of the hardware considerations. The bottom
of the LFCSP package has an exposed pad that must be soldered to a metal plate on the PCB for mechanical reasons and to DGND. The
metal plate of the PCB can be connected to ground. The 0.47 µF capacitor on the AVDD_REG and DVDD_REG pins should be placed
as close to the pins as possible. In noisy environments, an additional 1 nF capacitor can be added to IOVDD and AVDD.
1
2
3
P0.7/POR/SOUT
P0.6/IRQ2/SIN
P0.5/CTS/IRQ1
4
P0.4/RTS/ECLKO
5
P0.3/IRQ0/CS1
6
P0.2/MOSI1/SDA/SOUT
7
P0.1/SCLK1/SCL/SIN
24
AIN7/VBIAS0/
IEXC/
EXTREF2IN+
23
AIN6/IEXC
22
AIN5/IEXC
21
IREF
20
INT_REF
19
DAC
18
AVDD_REG
17
AVDD
16
AGND
12pF
12pF
15
VREF–
14
VREF+
13
GND_SW
44
P1.6/IRQ6/
PWM4/MOSI0
45
P1.7/IRQ7/
PWM5/CS0
46
P2.0/SCL/
UARTCLK
47
SWCLK
48
SWDIO
SWCLK
SWDIO
43
P1.5/IRQ5/
PWM3/SCLK0
42
P1.4/PWM2/
MISO0
41
P1.3/PWM1/
DSR
40
P1.2/PWM0/RI
39
P1.1/IRQ4/PWMTRIP/DTR
38
P1.0/IRQ3/PWMSYNC/EXTCLK
37
IOVDD
ADuCM360
25
AIN4/IEXC
26
AIN3
27
AIN2
28
AIN1
29
AIN0
30
DVDD_REG
DVDD
DGND
31
IOVDD
32
XTALI
33
XTALO
34
P2.2/BM
35
P2.1/SDA/UARTDCD
36
RESET
RESET
RESET
RESET
8
P0.0/MISO1
9
AIN11/VBIAS1
10
AIN10
11
AIN9/DACBUFF+
12
AIN8/EXTREF2IN–
0.47µF
0.47µF
0.1µF
150kΩ
GND
DGND
SWIO
TX
SWCLK
RX
5V USB
SWDIO
INTERFACE BOARD CONNECTOR
SWCLK
DVDD
DGND
DGND
0.1µF
AVDD
0.47µF
0.1µF
0.1µF
1µF
0.1µF
560Ω
1.6Ω
IN
OUT
EN
GND
DGND
DGND
DGND
AVDD
DVDD
AGND AGND AGND
4.7µF
4.7µF
ADP1720ARMZ-3.3
09743-100
Figure 15. Typical System Configuration