Datasheet

ADuCM360/ADuCM361 Data Sheet
Rev. B | Page 16 of 24
Table 13. SPI Slave Mode Timing
Parameter Description Min Typ Max Unit
t
CS
CS
to SCLK edge
62.5 ns
t
SL
SCLK low pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
SH
SCLK high pulse width
1
62.5 (SPIDIV + 1) × t
UCLK
ns
t
DAV
Data output valid after SCLK edge 49.1 ns
t
DSU
Data input setup time before SCLK edge 20.2 ns
t
DHD
Data input hold time after SCLK edge 10.1 ns
t
DF
Data output fall time 12 35.5 ns
t
DR
Data output rise time 12 35.5 ns
t
SR
SCLK rise time 12 35.5 ns
t
SF
SCLK fall time 12 35.5 ns
t
DOCS
Data output valid after CS
edge
25 ns
t
SFS
CS
high after SCLK edge
0 ns
1
t
UCLK
= 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
SCLK
(POLARITY = 0)
CS
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
t
SFS
MISO MSB BIT 6 TO BIT 1 LSB
MOSI MSB IN BIT 6 TO BIT 1 LSB IN
t
DHD
t
DSU
t
DAV
t
DR
t
DF
t
CS
0
9743-005
Figure 6. SPI Slave Mode Timing (Phase Mode = 1)
SCLK
(
POLARITY = 0)
CS
SCLK
(
POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
t
SFS
MISO
MSB BIT 6 TO BIT 1 LSB
MOSI MSB IN BIT 6 TO BIT 1 LSB IN
t
DHD
t
DSU
t
DAV
t
DR
t
DF
t
DOCS
t
CS
09743-006
Figure 7. SPI Slave Mode Timing (Phase Mode = 0)