Datasheet

Data Sheet ADuCM360/ADuCM361
Rev. B | Page 15 of 24
SPI TIMING SPECIFICATIONS
Table 12. SPI Master Mode Timing
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
SH
SCLK high pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
DAV
Data output valid after SCLK edge 0 35.5 ns
t
DOSU
Data output setup time before SCLK edge
1
(SPIDIV + 1) × t
UCLK
ns
t
DSU
Data input setup time before SCLK edge 58.7 ns
t
DHD
Data input hold time after SCLK edge 16 ns
t
DF
Data output fall time 12 35.5 ns
t
DR
Data output rise time 12 35.5 ns
t
SR
SCLK rise time 12 35.5 ns
t
SF
SCLK fall time 12 35.5 ns
1
t
UCLK
= 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
SCLK
(POLARITY = 0)
CS
1/2 SCLK
CYCLE
SCLK
(POLARITY = 1)
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
SH
t
CS
t
SL
3/4 SCLK
CYCLE
t
SFS
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DSU
t
DHD
09743-003
Figure 4. SPI Master Mode Timing (Phase Mode = 1)
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
SH
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DOSU
t
DSU
t
DHD
CS
1 SCLK CYCLE
t
CS
t
SL
1 SCLK CYCLE
t
SFS
09743-004
Figure 5. SPI Master Mode Timing (Phase Mode = 0)