Datasheet

ADuCM360/ADuCM361 Data Sheet
Rev. B | Page 14 of 24
I
2
C TIMING SPECIFICATIONS
The capacitive load for each I
2
C bus line (C
B
) is 400 pF maximum as per the I
2
C bus specifications. I
2
C timing is guaranteed by design, but
is not production tested.
Table 10. I
2
C Timing in Fast Mode (400 kHz)
Parameter Description Min Max Unit
t
L
Serial clock (SCL) low pulse width 1300 ns
t
H
SCL high pulse width 600 ns
t
SHD
Start condition hold time 600 ns
t
DSU
Data setup time 100 ns
t
DHD
Data hold time 0 ns
t
RSU
Setup time for repeated start 600 ns
t
PSU
Stop condition setup time 600 ns
t
BUF
Bus free time between a stop condition and a start condition 1.3
s
t
R
Rise time for both SCL and serial data (SDA) 20 + 0.1 C
B
300 ns
t
F
Fall time for both SCL and SDA 20 + 0.1 C
B
300 ns
t
SUP
Pulse width of suppressed spike 0 50 ns
Table 11. I
2
C Timing in Standard Mode (100 kHz)
Parameter Description Min Max Unit
t
L
SCL low pulse width 4.7 μs
t
H
SCL high pulse width 4.0 ns
t
SHD
Start condition hold time 4.7 μs
t
DSU
Data setup time 250 ns
t
DHD
Data hold time 0 μs
t
RSU
Setup time for repeated start 4.0 μs
t
PSU
Stop condition setup time 4.0 μs
t
BUF
Bus free time between a stop condition and a start condition 4.7 μs
t
R
Rise time for both SCL and SDA 1 μs
t
F
Fall time for both SCL and SDA 300 ns
SDA (I/O)
t
BUF
MSB LSB ACK MSB
1981
SCL (I)
PS
STOP
CONDITION
START
CONDITION
S(R)
REPEATED
START
t
SUP
t
R
t
F
t
F
t
R
t
H
t
L
t
SUP
t
DSU
t
DHD
t
RSU
t
DHD
t
DSU
t
SHD
t
PSU
09743-002
Figure 3. I
2
C-Compatible Interface Timing