Datasheet
ADuCM360/ADuCM361 Data Sheet
Rev. B | Page 10 of 24
8
System calibration at a specific gain removes the error at this gain.
9
Input current measured with one ADC measuring a channel. If both ADCs measure the same input channel, the input current increases (approximately doubles).
10
Measured using the box method.
11
Reference DAC linearity is calculated using a reduced code range of 0x0AB to 0xF30.
12
Endurance is qualified to 10,000 cycles as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
13
Retention lifetime equivalent at junction temperature (T
J
) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.
14
Voltage input levels are relevant only if driving XTAL input from a voltage source. If a crystal is connected directly, the internal crystal interface determines the
common-mode voltage.
15
Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA.
16
Total I
DD
for ADC includes figures for PGA ≥ 32, input buffers, digital interface, and the Σ-Δ modulator.
RMS NOISE RESOLUTION OF ADC0 AND ADC1
Internal Reference (1.2 V)
Table 2 through Table 5 provide rms noise specifications for ADC0 and ADC1 using the internal reference (1.2 V). Table 2 and Tabl e 3 list
the rms noise for both ADCs with various gain and output update rate values. Table 4 and Table 5 list the typical output rms noise effective
number of bits (ENOB) in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown
in parentheses.)
Table 2. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 1, 2, 4, 8, and 16
RMS Noise (µV)
Update
Rate (Hz)
Chop/Sinc
ADCFLT
Register
Value
Gain = 1,
±V
REF
,
ADCxMDE = 0x01
Gain = 2,
±500 mV,
ADCxMDE = 0x11
Gain = 4,
±250 mV,
ADCxMDE = 0x21
Gain = 8,
±125 mV,
ADCxMDE = 0x31
Gain = 16,
±62.5 mV,
ADCxMDE = 0x41
3.53 On/Sinc3 0x8D7C 1.05 0.45 0.23 0.135 0.072
30
Off/Sinc3
0x007E
2.1
1.37
0.63
0.37
0.22
50 Off/Sinc3 0x007D 3.7 1.6 0.83 0.47 0.29
100 Off/Sinc3 0x004D 5.45 2.41 1.13 0.63 0.38
488 Off/Sinc4 0x100F 10 4.7 2.2 1.3 0.79
976 Off/Sinc4 0x1007 13.5 6.5 3.3 1.7 1.1
1953 Off/Sinc4 0x1003 19.3 10 4.7 2.6 1.55
3906 Off/Sinc4 0x1001 67.0 36 16.6 8.8 4.9
Table 3. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 32, 64, and 128
RMS Noise (µV)
Update
Rate (Hz)
Chop/Sinc
ADCFLT
Register
Value
Gain = 32,
1
±62.5 mV,
ADCxMDE =
0x49
Gain = 32,
1, 2
±22.18 mV,
ADCxMDE =
0x51
Gain = 64,
3
±15.625 mV,
ADCxMDE =
0x59
Gain = 64,
3,
4
±10.3125 mV,
ADCxMDE =
0x61
Gain = 128,
5
±7.8125 mV,
ADCxMDE =
0x69
Gain = 128,
5, 6
±3.98 mV,
ADCxMDE =
0x71
3.53 On/Sinc3 0x8D7C 0.067 0.064 0.073 0.055 0.058 0.052
30
Off/Sinc3
0x007E
0.202
0.2
0.196
0.16
0.174
0.155
50 Off/Sinc3 0x007D 0.24 0.24 0.25 0.21 0.21 0.2
100 Off/Sinc3 0x004D 0.35 0.32 0.36 0.27 0.31 0.25
488 Off/Sinc4 0x100F 0.7 0.67 0.71 0.58 0.62 0.57
976 Off/Sinc4 0x1007 0.99 0.91 1.01 0.74 0.83 0.7
1953
Off/Sinc4
0x1003
1.78
1.3
1.48
1.15
1.25
1.0
3906 Off/Sinc4 0x1001 6.44 2.68 3.59 1.4 2.2 1.4
1
ADCxMDE = 0x49 sets the PGA for a gain of 16 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x51 sets the PGA for a gain of 32 with the modulator gain off. ADCxMDE = 0x49 has slightly higher noise but supports a wider input range.
2
If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is ±17.5 mV.
3
ADCxMDE = 0x59 sets the PGA for a gain of 32 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x61 sets the PGA for a gain of 64 with the modulator gain off. ADCxMDE = 0x59 has slightly higher noise but supports a wider input range.
4
If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is ±8.715 mV.
5
ADCxMDE = 0x69 sets the PGA for a gain of 64 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x71 sets the PGA for a gain of 128 with the modulator gain off. ADCxMDE = 0x69 has slightly higher noise but supports a wider input range.
6
If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is ±3.828 mV.