Datasheet

Data Sheet ADuC845/ADuC847/ADuC848
Rev. C | Page 97 of 108
Table 66. EXTERNAL DATA MEMORY WRITE CYCLE Parameter
12.58 MHz Core Clock 6.29 MHz Core Clock
Min Max Min Max Unit
t
WLWH
WR Pulse Width
65 130 ns
t
AVLL
Address Valid After ALE Low 60 120 ns
t
LLAX
Address Hold After ALE Low 65 135 ns
t
LLWL
ALE Low to
RD or WR Low
130 260 ns
t
AVWL
Address Valid to
RD or WR Low
190 375 ns
t
QVWX
Data Valid to
WR Transition
60 120 ns
t
QVWH
Data Setup Before
WR
120 250 ns
t
WHQX
Data and Address Hold After
WR
380 755 ns
t
WHLH
RD or WR High to ALE High
60 125 ns
04741-079
ALE (O)
PORT 2 (O)
t
WHLH
t
WLWH
t
LLWL
t
AVWL
t
LLAX
t
AVLL
t
QVWX
t
QVWH
t
WHQX
A0�A7 DATA
A16�A23 V8 A15
PSEN (O)
WR (O)
Figure 74. External Data Memory Write Cycle
Table 67. I
2
C-C OMPATIBLE INTERFACE TIMING Parameter
Parameter
Min Max Unit
t
L
SCLCK Low Pulse Width
1.3
µs
t
H
SCLCK High Pulse Width 0.6 µs
t
SHD
Start Condition Hold Time 0.6 µs
t
DSU
Data Setup Time 100 µs
t
DHD
Data Hold Time 0.9 µs
t
RSU
Setup Time for Repeated Start 0.6 µs
t
PSU
Stop Condition Setup Time 0.6 µs
t
BUF
Bus Free Time Between a Stop Condition and a Start Condition 1.3 µs
t
R
Rise Time of Both SCLCK and SDATA 300 ns
t
F
Fall Time of Both SCLCK and SDATA 300 ns
t
SUP
1
Pulse Width of Spike Suppressed 50 ns
____________________________________________
1
Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.