Datasheet

ADuC845/ADuC847/ADuC848 Data Sheet
Rev. C | Page 96 of 108
Table 65. EXTERNAL DATA MEMORY READ CYCLE Parameter
12.58 MHz Core Clock 6.29 MHz Core Clock
Min Max Min Max Unit
t
RLRH
RD Pulse Width
60 125 ns
t
AVLL
Address Valid After ALE Low 60 120 ns
t
LLAX
Address Hold After ALE Low 145 290 ns
t
RLDV
RD Low to Valid Data In
48 100 ns
t
RHDX
Data and Address Hold After
RD
0 0 ns
t
RHDZ
Data Float After
RD
150 625 ns
t
LLDV
ALE Low to Valid Data In 170 350 ns
t
AVDV
Address to Valid Data In 230 470 ns
t
LLWL
ALE Low to
RD or WR Low
130 255 ns
t
AVWL
Address Valid to
RD or WR Low
190 375 ns
t
RLAZ
RD Low to Address Float
15
35
ns
t
WHLH
RD or WR High to ALE High
60 120 ns
04741-078
ALE (O)
PORT 0 (I/O)
PORT 2 (O)
t
WHLH
t
LLDV
t
LLWL
t
RLRH
t
AVWL
t
LLAX
t
AVLL
t
RLAZ
t
RHDX
t
RHDZ
t
AVDV
A0�A7 (OUT) DATA (IN)
A16�A23 A8 A15
t
RLDV
PSEN (O)
RD (O)
Figure 73. External Data Memory Read Cycle