Datasheet

Data Sheet ADuC845/ADuC847/ADuC848
Rev. C | Page 69 of 108
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within a
reasonable amount of time if the ADuC845/ADuC847/
ADuC848 enters an erroneous state, possibly due to a program-
ming error or electrical noise. The watchdog function can be
disabled by clearing the WDE (watchdog enable) bit in the
watchdog control (WDCON) SFR. When enabled, the
watchdog circuit generates a system reset or interrupt (WDS) if
the user program fails to set the WDE bit within a predetermined
amount of time (see the PRE3…0 bits in Table 44). The
watchdog timer is clocked from the 32 kHz external crystal
connected between the XTAL1 and XTAL2 pins. The WDCOM
SFR can be written only by user software if the double write
sequence described in WDWR is initiated on every write access
to the WDCON SFR.
WDCON—Watchdog Control Register
SFR Address: C0H
Power-On Default: 10H
Bit Addressable: Yes
Table 44. WDCON SFR Bit Designations
Bit No. Name Description
7, 6, 5, 4 PRE3, PRE2, PRE1, PRE0 Watchdog Timer Prescale Bits.
The watchdog timeout period is given by the equation
t
WD
= (2
PRE
× (2
9
/ f
XTAL
)) (0 ≤ PRE ≤ 7; f
XTAL
= 32.768 kHz)
PRE3 PRE2 PRE1 PRE0 Timeout Period (ms) Action
0 0 0 0 15.6 Reset or interrupt
0 0 0 1 31.2 Reset or interrupt
0 0 1 0 62.5 Reset or interrupt
0 0 1 1 125 Reset or interrupt
0
1
0
0
250
Reset or interrupt
0 1 0 1 500 Reset or interrupt
0 1 1 0 1000 Reset or interrupt
0 1 1 1 2000 Reset or interrupt
1 0 0 0 0.0 Immediate reset
PRE3–PRE0 > 1000b Reserved. Not a valid selection.
3
WDIR
Watchdog Interrupt Response Enable Bit.
If this bit is set by the user, the watchdog generates an interrupt response instead of a system reset
when the watchdog timeout period expires. This interrupt is not disabled by the CLR EA instruction,
and it is also a fixed, high priority interrupt. If the watchdog timer is not being used to monitor the
system, it can be used alternatively as a timer. The prescaler is used to set the timeout period in
which an interrupt is generated.
2 WDS Watchdog Status Bit.
Set by the watchdog controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
1 WDE Watchdog Enable Bit.
Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within
the watchdog timeout period, the watchdog timer generates a reset or interrupt, depending on
WDIR.
Cleared under the following conditions: user writes 0; watchdog reset (WDIR = 0); hardware reset;
PSM interrupt.
0 WDWR Watchdog Write Enable Bit.
Writing data to the WDCON SFR involves a double instruction sequence. Global interrupts must first
be disabled. The WDWR bit is set with the very next instruction, a write to the WDCON SFR. For
example:
CLR EA ;Disable Interrupts while configuring to WDT
SETB WDWR ;Allow Write to WDCON
MOV WDCON, #72H ;Enable WDT for 2.0s timeout
SETB EA ;Enable Interrupts again (if required)