Datasheet

ADuC845/ADuC847/ADuC848 Data Sheet
Rev. C | Page 46 of 108
SF (ADC SINC FILTER CONTROL REGISTER)
The SF register is used to configure the decimation factor for the ADC, and therefore, has a direct influence on the ADC throughput rate.
SFR Address: D4H
Power-On Default: 45H
Bit Addressable: No
Table 28. Sinc Filter SFR Bit Designations
SF.7 SF.6 SF.5 SF.4 SF.3 SF.2 SF.1 SF.0
0 1 0 0 0 1 0 1
The bits in this register set the decimation factor of the ADC. This has a direct bearing on the throughput rate of the ADC along with the
chop setting. The equations used to determine the ADC throughput rate are
Fadc (Chop On) =
SFword××83
1
× 32.768 kHz
where SFword is in decimal.
Fadc (Chop Off) =
SFword×8
1
× 32.768 kHz
where SFword is in decimal.
Table 29. SF SFR Bit Examples
Chop Enabled (ADCMODE.3 = 0)
SF (Decimal)
SF (Hexadecimal)
Fadc (Hz)
Tadc (ms)
Tsettle (ms)
13
1
0D 105.3 9.52 19.04
69
45
19.79
50.53
101.1
82 52 16.65 60.06 120.1
255 FF 5.35 186.77 373.54
Chop Disabled (ADCMODE.3 = 1)
SF (Decimal) SF (Hexadecimal) Fadc (Hz) Tadc (ms) Tsettle (ms)
3
03
1365.3
0.73
2.2
69 45 59.36 16.84 50.52
82 52 49.95 20.02 60.06
255 FF 16.06 62.25 186.8
1
With chop enabled, if an SF word smaller than 13 is written to this SF register, the filter automatically defaults to 13.
During ADC calibration, the user-programmed value of SF word is used. The SF word does not default to the maximum setting (255) as it
did on previous MicroConverter® products. However, for optimum calibration results, it is recommended that the maximum SF word be set.