Datasheet

ADuC845/ADuC847/ADuC848 Data Sheet
Rev. C | Page 28 of 108
This offset is removed by performing a running average of 2.
This average by 2 means that the settling time to any change in
programming of the ADC is twice the normal conversion time,
while an asynchronous step change on the analog input is not
fully reflected until the third subsequent output. See Figure 13.
ADC
ADC
SETTLE
t
f
t  2
2
The allowable range for SF (chop enabled) is 13 to 255 with
a default of 69 (45H). The corresponding conversion rates,
rms and peak-to-peak noise performances are shown in
Table 10, Table 11, Table 12, and Table 13. The numbers are
typical and generated at a differential input voltage of 0 V
and a common-mode voltage of 2.5 V. Note that the con-
version time increases by 0.732 ms for each increment in SF.
SAMPLE 1
NO/INVALID
OUTPUT
SAMPLE 2 SAMPLE 3 SAMPLE 4 SAMPLE 5 SAMPLE 6
SAMPLE 1 + SAMPLE 2
VALID OUTPUT
2
SAMPLE 5 + SAMPLE 6
VALID OUTPUT
2
SAMPLE 2 + SAMPLE 3
VALID OUTPUT
2
SYNCHRONOUS CHANGE
(I.E. CHANNEL CHANGE)
SAMPLE 4 + SAMPLE 5
VALID OUTPUT
2
SAMPLE 3 + SAMPLE 4
NO OUTPUT
2
04741-012
Figure 13. ADC Settling Time Following a Synchronous Change with
Chop Enabled
SAMPLE 1
NO OUTPUT
SAMPLE 2 SAMPLE 3 SAMPLE 4 SAMPLE 5 SAMPLE 6
SAMPLE 1 + SAMPLE 2
VALID OUTPUT
2
SAMPLE 5 + SAMPLE 6
VALID OUTPUT
2
SAMPLE 2 + SAMPLE 3
VALID OUTPUT
2
ASYNCHRONOUS CHANGE
(I.E. DISCONTINUOUS INPUT CHANGE)
SAMPLE 4 + SAMPLE 5
UNSETTLED OUTPUT
2
SAMPLE 3 + SAMPLE 4
UNSETTLED OUTPUT
2
04741-014
Figure 14. ADC Settling Time Following an Asynchronous Change with
Chop Enabled