Datasheet

Data Sheet ADuC845/ADuC847/ADuC848
Rev. C | Page 103 of 108
Table 72. UART TIMING (SHIFT REGISTER MODE) Parameter
12.58 MHz Core_Clk Variable Core_Clk
Min Typ Max Min Typ Max Unit
TXLXL Serial Port Clock Cycle Time 954 12t
core
ns
TQVXH Output Data Setup to Clock 662 ns
TDVXH Input Data Setup to Clock 292 ns
TXHDX Input Data Hold After Clock 0 ns
TXHQX Output Data Hold After Clock 22 ns
SET RI
OR
SET TI
BIT 6
t
XLXL
TxD
(OUTPUT CLOCK)
RxD
(OUTPUT DATA)
RxD
(INPUT DATA)
BIT 1
LSB
LSB
BIT 1
BIT 6 MSB
t
XHQX
t
QVXH
t
DVXH
t
XHDX
04741-086
Figure 80. UART Timing in Shift Register Mode