Datasheet

Data Sheet ADuC845/ADuC847/ADuC848
Rev. C | Page 99 of 108
Table 68. SPI MASTER MODE TIMING (CPHA = 1) Parameter
Min Typ Max Unit
t
SL
SCLOCK Low Pulse Width
1
635 ns
t
SH
SCLOCK High Pulse Width
1
635 ns
t
DAV
Data Output Valid After SCLOCK Edge
50
ns
t
DSU
Data Input Setup Time Before SCLOCK Edge 100 ns
t
DHD
Data Input Hold Time After SCLOCK Edge 100 ns
t
DF
Data Output Fall Time 10 25 ns
t
DR
Data Output Rise Time 10 25 ns
t
SR
SCLOCK Rise Time 10 25 ns
t
SF
SCLOCK Fall Time 10 25 ns
____________________________________________
1
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 1.57 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
SCLOCK
(CPOL = 0)
t
DSU
SCLOCK
(CPOL = 1)
MOSI
MISO
MSB
LSB
LSB IN
BITS 6–1
BITS 6–1
t
DHD
t
DR
t
DAV
t
DF
t
SH
t
SL
t
SR
t
SF
MSB IN
04741-081
Figure 76. SPI Master Mode Timing (CHPA = 1)