Datasheet

ADuC845/ADuC847/ADuC848 Data Sheet
Rev. C | Page 56 of 108
PWMCON PWM Control SFR
SFR Address: AEH
Power-On Default: 00H
Bit Addressable: No
Table 34. PWMCON PWM Control SFR
Bit No. Name Description
7 ––– Not Implemented. Write Don’t Care.
6, 5, 4 PWM2, PWM1, PWM0 PMW Mode Selection.
PWM2 PWM1 PWM0
0 0 0 Mode 0: PWM disabled.
0 0 1 Mode 1: Single 16-bit output with programmable pulse and cycle time.
0 1 0 Mode 2: Twin 8-bit outputs.
0 1 1 Mode 3: Twin 16-bit outputs.
1
0
0
Mode 4:
Dual 16-bit pulse density outputs.
1 0 1 Mode 5: Dual 8-bit outputs.
1 1 0 Mode 6: Dual 16-bit pulse density RZ outputs.
1 1 1 Mode 7: PWM counter reset with outputs not used.
3, 2 PWS1, PWS0 PWM Clock Source Divider.
PWS1 PWS0
0 0 Selected clock.
0 1 Selected clock divided by 4.
1 0 Selected clock divided by 16.
1 1 Selected clock divided by 64.
1, 0 PWC1, PWC0 PWM Clock Source Selection.
PWC1 PWC0
0 0 F
XTAL
/15 (2.184 kHz).
0 1 F
XTAL
(32.768 kHz).
1 0 External input on P2.7.
1
1
F
VCO
(12.58 MHz).
PWM Pulse Width High Byte (PWM0H)
SFR Address: B2H
Power-On Default: 00H
Bit Addressable: No
Table 35. PWM0H: PWM Pulse Width High Byte
PWM0H.7 PWM0H.6 PWM0H.5 PWM0H.4 PWM0H.3 PWM0H.2 PWM0H.1 PWM0H.0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
PWM Pulse Width Low Byte (PWM0L)
SFR Address: B1H
Power-On Default: 00H
Bit Addressable: No
Table 36. PWM0L: PWM Pulse Width Low Byte
PWM0L.7 PWM0L.6 PWM0L.5 PWM0L.4 PWM0L.3 PWM0L.2 PWM0L.1 PWM0L.0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W