Datasheet

Data Sheet ADuC845/ADuC847/ADuC848
Rev. C | Page 65 of 108
SPICON—SPI Control Register
SFR Address: F8H
Power-On Default: 05H
Bit Addressable: Yes
Table 41. SPICON SFR Bit Designations
Bit No. Name Description
7
ISPI
SPI Interrupt Bit.
Set by the MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
6 WCOL Write Collision Error Bit.
Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
5 SPE SPI Interface Enable Bit.
Set by user code to enable SPI functionality.
Cleared by user code to enable standard Port 2 functionality.
4 SPIM SPI Master/Slave Mode Select Bit.
Set by user code to enable master mode operation (SCLOCK is an output).
Cleared by user code to enable slave mode operation (SCLOCK is an input).
3 CPOL
1
Clock Polarity Bit.
Set by user code to enable SCLOCK idle high.
Cleared by user code to enable SCLOCK idle low.
2 CPHA
1
Clock Phase Select Bit.
Set by user code if the leading SCLOCK edge is to transmit data.
Cleared by user code if the trailing SCLOCK edge is to transmit data.
1, 0 SPR1, SPR0 SPI Bit-Rate Bits.
SPR1 SPR0 Selected Bit Rate
0 0 f
core
/2
0 1 f
core
/4
1
0
f
core
/8
1 1 f
core
/16
1
The CPOL and CPHA bits should both contain the same values for master and slave devices.
Note that both SPI and I
2
C use the same ISR (Vector Address 3BH); therefore, when using SPI and I
2
C simultaneously, it is necessary to
check the interfaces following an interrupt to determine which one caused the interrupt.
SPIDAT: SPI Data Register
SFR Address: 7FH
Power-On Default: 00H
Bit Addressable: No