Datasheet

Data Sheet ADuC845/ADuC847/ADuC848
Rev. C | Page 95 of 108
TIMING SPECIFICATIONS
AC inputs during testing are driven at DV
DD
– 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at V
IH
min for
Logic 1 and V
IL
max for Logic 0 as shown in Figure 72.
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a
100 mV change from the loaded V
OH
/V
OL
level occurs as shown in Figure 72.
C
LOAD
for all outputs = 80 pF, unless otherwise noted.
AV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications T
MIN
to T
MAX
, unless otherwise
noted.
Table 64. CLOCK INPUT (External Clock Driven XTAL1) Parameter
32.768 kHz External Crystal
Min Typ Max Unit
t
CK
XTAL1 Period 30.52 µs
t
CKL
XTAL1 Width Low 6.26 µs
t
CKH
XTAL1 Width High
6.26
µs
t
CKR
XTAL1 Rise Time 9 ns
t
CKF
XTAL1 Fall Time 9 ns
1/t
CORE
Core Clock Frequency
1
0.098 1.57 12.58 MHz
t
CORE
Core Clock Period
2
0.636 µs
t
CYC
Machine Cycle Time
3
10.2 0.636 0.08 µs
1
ADuC845/ADuC847/ADuC848 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 12.58 MHz internal clock
for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
2
This number is measured at the default Core_Clk operating frequency of 1.57 MHz.
3
ADuC845/ADuC847/ADuC848 machine cycle time is nominally defined as 1/Core_Clk.
DV
DD
– 0.5V
0.45V
0.2DV
DD
+ 0.9V
TEST POINTS
0.2DV
DD
– 0.1V
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINTS
V
LOAD
– 0.1V
V
LOAD
V
LOAD
– 0.1V
04741-077
Figure 72. Timing Waveform Characteristics