Datasheet

ADuC845/ADuC847/ADuC848 Data Sheet
Rev. C | Page 84 of 108
T3FD—Timer 3 Fractional Divider Register
See Table 57 for values.
SFR Address: 9DH
Power-On Default: 00H
Bit Addressable: No
Table 56. T3FD SFR Bit Designations
Bit No. Name Description
7 ---- Not Implemented. Write Don’t Care.
6
----
Not Implemented. Write Don’t Care.
5 T3FD.5 Timer 3 Fractional Divider Bit 5.
4 T3FD.4 Timer 3 Fractional Divider Bit 4.
3 T3FD.3 Timer 3 Fractional Divider Bit 3.
2 T3FD.2 Timer 3 Fractional Divider Bit 2.
1 T3FD.1 Timer 3 Fractional Divider Bit 1.
0 T3FD.0 Timer 3 Fractional Divider Bit 0.
Table 57. Common Baud Rates Using Timer 3 with a 12.58 MHz PLL Clock
Ideal Baud CD DIV T3CON T3FD % Error
230400 0 1 81H 2DH 0.18
115200 0 2 82H 2DH 0.18
115200 1 1 81H 2DH 0.18
57600 0 3 83H 2DH 0.18
57600 1 2 82H 2DH 0.18
57600 2 1 81H 2DH 0.18
38400 0 4 84H 12H 0.12
38400 1 3 83H 12H 0.12
38400 2 2 82H 12H 0.12
38400 3 1 81H 12H 0.12
19200 0 5 85H 12H 0.12
19200
1
4
84H
12H
0.12
19200 2 3 83H 12H 0.12
19200 3 2 82H 12H 0.12
19200 4 1 81H 12H 0.12
9600 0 6 86H 12H 0.12
9600 1 5 85H 12H 0.12
9600 2 4 84H 12H 0.12
9600 3 3 83H 12H 0.12
9600 4 2 82H 12H 0.12
9600 5 1 81H 12H 0.12