Datasheet

ManualsBrandsANALOG DEVICES ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LFCSP 56 VQ (8x8) 8-Bit 12.58 MHz I/O number 34

Data Sheet ADuC845/ADuC847/ADuC848

Rev. C | Page 35 of 108

Therefore, the full-scale endpoint calibration automatically

subtracts the offset calibration error, it is advisable to perform

an offset calibration at the same gain range as that used for full-

scale calibration. There is no penalty to the full-scale calibration

in redoing the zero-scale calibration at the required PGA range

because the full-scale calibration has very good matching at all

the PGA ranges.

This procedure also applies when chop is disabled.

Note that for internal calibration to be effective, the AIN− pin

should be held at a steady voltage, within the allowable common-

mode range to keep it from floating during calibration.

System Calibration Example

With chop enabled, a system zero-scale or offset calibration

should never be required. However, if a full-scale or gain

calibration is required for any reason, use the following typical

procedure for doing so.

1. Apply a differential voltage of 0 V to the selected analog

inputs (AIN+ to AIN−) that are held at a common-mode

voltage.

Perform a system zero-scale or offset calibration by setting

the MD2...0 bits in the ADCMODE register to 110B.

2. Apply a full-scale differential voltage across the ADC

inputs again at the same common-mode voltage.

Perform a system full-scale or gain calibration by setting

the MD2...0 bits in the ADCMODE register to 111B.

Perform a system calibration at the required PGA range to be

used since the ADC scales to the differential voltages that are

applied to the ADC during the calibration routines.

In bipolar mode, the zero-scale calibration determines the mid-

scale point of the ADC (800000H) or 0 V.

PROGRAMMABLE GAIN AMPLIFIER

The primary ADC incorporates an on-chip programmable gain

amplifier (PGA). The PGA can be programmed through eight

different ranges, which are programmed via the range bits (RN0

to RN2) in the ADC0CON1 register. With an external 2.5 V

reference applied, the unipolar ranges are 0 mV to 20 mV, 0 mV

to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 m V,

0 mV to 640 mV, 0 V to 1.28 V and 0 V to 2.56 V, while in

bipolar mode the ranges are ±20 mV, ±40 mV, ±80 mV, ±160 m V,

±320 mV, ±64 0 m V, ±1.28 V, and ±2.56 V. These ranges should

appear on the input to the on-chip PGA. The ADC range-

matching specification of 2 µV (typical with chop enabled)

means that calibration need only be carried out on a single

range and need not be repeated when the ADC range is

changed. This is a significant advantage compared to similar

mixed-signal solutions available on the market. The auxiliary

(ADuC845 only) ADC does not incorporate a PGA, and the

gain is fixed at 0 V to 2.50 V in unipolar mode, and ±2.50 V in

bipolar mode.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog inputs of the ADuC845/ADuC847/ADuC848 can

accept either unipolar or bipolar input voltage ranges. Bipolar

input ranges do not imply that the part can handle negative

voltages with respect to system AGND, but rather with respect

to the negative reference input. Unipolar and bipolar signals on

the AIN(+) input on the ADC are referenced to the voltage on

the respective AIN(−) input. AIN(+) and AIN(−) refer to the

signals seen by the ADC.

For example, if AIN(−) is biased to 2.5 V (tied to the external

reference voltage) and the ADC is configured for a unipolar

analog input range of 0 mV to >20 mV, the input voltage range

on AIN(+) is 2.5 V to 2.52 V. On the other hand, if AIN(−) is

biased to 2.5 V (again the external reference voltage) and the

ADC is configured for a bipolar analog input range of ±1.28 V,

the analog input range on the AIN(+) is 1.22 V to 3.78 V, that is,

2.5 V ± 1.28 V.

The mod

es of operation for the ADC are fully differential mode

or pseudo differential mode. In fully differential mode, AIN1 to

AIN2 are one differential pair, and AIN3 to AIN4 are another

pair (AIN5 to AIN6, AIN7 to AIN8, and AIN9 to AIN10 are the

others). In differential mode, all AIN(−) pin names imply the

negative analog input of the selected differential pair, that is,

AIN2, AIN4, AIN6, AIN8, AIN10. The term AIN(+) implies

the positive input of the selected differential pair, that is, AIN1,

AIN3, AIN5, AIN7, AIN9. In pseudo differential mode, each

analog input is paired with the AINCOM pin, which can be

biased up or tied to AGND. In this mode, the AIN(−) implies

AINCOM, and AIN(+) implies any one of the ten analog input

channels.

The configuration of the inputs (unipolar vs. bipolar) is shown

in Figure 17.

AIN1

INPUT 1

ADuC845/ADuC847/ADuC848

CSP PACKAGE

ADuC845/ADuC847/ADuC848

CSP PACKAGE

INPUT 2

INPUT 3

INPUT 4

INPUT 5

INPUT 6

INPUT 7

INPUT 8

INPUT 9

INPUT 10

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AINCOM