Datasheet

ADuC841/ADuC842/ADuC843
Rev. 0 | Page 83 of 88
Parameter
SPI MASTER MODE TIMING (CPHA = 0) Min Typ Max Unit
t
SL
SCLOCK Low Pulse Width
1
476 ns
t
SH
SCLOCK High Pulse Width
1
476 ns
t
DAV
Data Output Valid after SCLOCK Edge 50 ns
t
DOSU
Data Output Setup before SCLOCK Edge 150 ns
t
DSU
Data Input Setup Time before SCLOCK Edge 100 ns
t
DHD
Data Input Hold Time after SCLOCK Edge 100 ns
t
DF
Data Output Fall Time 10 25 ns
t
DR
Data Output Rise Time 10 25 ns
t
SR
SCLOCK Rise Time 10 25 ns
t
SF
SCLOCK Fall Time 10 25 ns
1
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
SCLOCK
(CPOL = 0)
t
DSU
SCLOCK
(CPOL = 1)
MOSI
MISO
MSB
LSB
LSB IN
BITS 6–1
BITS 6–1
t
DHD
t
DR
t
DAV
t
DF
t
DOSU
t
SH
t
SL
t
SR
t
SF
MSB IN
03260-0-093
Figure 92. SPI Master Mode Timing (CPHA = 0)