Datasheet

ADuC841/ADuC842/ADuC843
Rev. 0 | Page 81 of 88
Parameter
I
2
C COMPATIBLE INTERFACE TIMING Min Max Unit
t
L
SCLOCK Low Pulse Width 1.3 µs
t
H
SCLOCK High Pulse Width 0.6 µs
t
SHD
Start Condition Hold Time 0.6 µs
t
DSU
Data Setup Time 100 µs
t
DHD
Data Hold Time 0.9 µs
t
RSU
Setup Time for Repeated Start 0.6 µs
t
PSU
Stop Condition Setup Time 0.6 µs
t
BUF
Bus Free Time between a Stop Conditionand a Start Condition 1.3 µs
t
R
Rise Time of Both SCLOCK and SDATA 300 ns
t
F
Fall Time of Both SCLOCK and SDATA 300 ns
t
SUP
1
Pulse Width of Spike Suppressed 50 ns
1
Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.
MSB
t
BUF
SDATA (I/O)
SCLK (I)
STOP
CONDITION
START
CONDITION
REPEATED
START
LSB ACK MSB
1 2-7 8 9 1
S(R)
PS
t
PSU
t
DSU
t
SHD
t
DHD
t
SUP
t
DSU
t
DHD
t
H
t
SUP
t
L
t
RSU
t
R
t
R
t
F
t
F
03260-0-091
Figure 90. I
2
C Compatible Interface Timing