Datasheet

ADuC841/ADuC842/ADuC843
Rev. 0 | Page 80 of 88
Parameter 16 MHz Core Clk 8 MHz Core Clock
EXTERNAL DATA MEMORY WRITE CYCLE Min Max Min Max Unit
t
WLWH
WR
Pulse Width
65 130 ns
t
AVLL
Address Valid after ALE Low 60 120 ns
t
LLAX
Address Hold after ALE Low 65 135 ns
t
LLWL
ALE Low to
RD
or
WR
Low
130 260 ns
t
AVWL
Address Valid to
RD
or
WR
Low
190 375 ns
t
QVWX
Data Valid to
WR
Transition
60 120 ns
t
QVWH
Data Setup before
WR
120 250 ns
t
WHQX
Data and Address Hold after
WR
380 755 ns
t
WHLH
RD
or
WR
High to ALE High
60 125 ns
03260-0-088
ALE (O)
PORT 2 (O)
t
WHLH
t
WLWH
t
LLWL
t
AVWL
t
LLAX
t
AVLL
t
QVWX
t
QVWH
t
WHQX
A0  A7 DATA
A16
 A23 V8 A15
PSEN (O)
WR (O)
Figure 89. External Data Memory Write Cycle