Datasheet
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 79 of 88
Parameter 16 MHz Core Clk 8 MHz Core Clock
EXTERNAL DATA MEMORY READ CYCLE Min Max Min Max Unit
t
RLRH
RD
Pulse Width
60 125 ns
t
AVLL
Address Valid after ALE Low 60 120 ns
t
LLAX
Address Hold after ALE Low 145 290 ns
t
RLDV
RD
Low to Valid Data In
48 100 Ns
t
RHDX
Data and Address Hold after
RD
0 0 ns
t
RHDZ
Data Float after
RD
150 625 ns
t
LLDV
ALE Low to Valid Data In 170 350 ns
t
AVDV
Address to Valid Data In 230 470 ns
t
LLWL
ALE Low to
RD
or
WR
Low
130 255 ns
t
AVWL
Address Valid to
RD
or
WR
Low
190 375 ns
t
RLAZ
RD
Low to Address Float
15 35 ns
t
WHLH
RD
or
WR
High to ALE High
60 120 ns
03260-0-087
ALE (O)
PORT 0 (I/O)
PORT 2 (O)
t
WHLH
t
LLDV
t
LLWL
t
RLRH
t
AVWL
t
LLAX
t
AVLL
t
RLAZ
t
RHDX
t
RHDZ
t
AVDV
A0
A7 (OUT) DATA (IN)
A16
A23 A8 A15
t
RLDV
PSEN (O)
RD (O)
Figure 88. External Data Memory Read Cycle