Datasheet

ADuC841/ADuC842/ADuC843
Rev. 0 | Page 49 of 88
Bit No. Name Description
2 I2CRS I
2
C Reset Bit (Slave Mode Only).
Set by the user to reset the I
2
C interface.
Cleared by the user code for normal I
2
C operation.
1 I2CTX I
2
C Direction Transfer Bit (Slave Mode Only).
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
0 I2CI I
2
C Interrupt Bit (Slave Mode Only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below).
I2CADD I
2
C Address Register
Function Holds the first I
2
C peripheral address for the part. It may be overwritten by user code. Application Note
uC001 at www.analog.com/microconverter describes the format of the I
2
C standard 7-bit address in
detail.
SFR Address 9BH
Power-On Default 55H
Bit Addressable No
I2CADD1 I
2
C Address Register
Function Holds the second I
2
C peripheral address for the part. It may be overwritten by user code.
SFR Address 91H
Power-On Default 7FH
Bit Addressable No
I2CADD2 I
2
C Address Register
Function Holds the third I
2
C peripheral address for the part. It may be overwritten by user code.
SFR Address 92H
Power-On Default 7FH
Bit Addressable No
I2CADD3 I
2
C Address Register
Function Holds the fourth I
2
C peripheral address for the part. It may be overwritten by user code.
SFR Address 93H
Power-On Default 7FH
Bit Addressable No
I2CDAT I
2
C Data Register
Function Written by the user to transmit data over the I
2
C interface or read by user code to read data just
received by the I
2
C interface. Accessing I2CDAT automatically clears any pending I
2
C interrupt and
the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle.
SFR Address 9AH
Power-On Default 00H
Bit Addressable No
The main features of the MicroConverter I
2
C interface are
Only two bus lines are required: a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I
2
C master can communicate with multiple slave
devices. Because each slave device has a unique 7-bit
address, single master/slave relationships can exist at all
times even in a multislave environment.
Ability to respond to four separate addresses when
operating in slave mode.