Datasheet

ADuC841/ADuC842/ADuC843
Rev. 0 | Page 46 of 88
SPICON SPI Control Register
SFR Address F8H
Power-On Default 04H
Bit Addressable Yes
Table 18. SPICON SFR Bit Designations
Bit No. Name Description
7 ISPI SPI Interrupt Bit.
Set by the MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
6 WCOL Write Collision Error Bit.
Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
5 SPE SPI Interface Enable Bit.
Set by the user to enable the SPI interface.
Cleared by the user to enable the I
2
C pins, this is not requiredto enable the I
2
C interface if the MSPI bit is set in
CFG841/CFG842. In this case, the I
2
C interface is automatically enabled.
4 SPIM SPI Master/Slave Mode Select Bit.
Set by the user to enable master mode operation (SCLOCK is an output).
Cleared by the user to enable slave mode operation (SCLOCK is an input).
3 CPOL
1
Clock Polarity Select Bit.
Set by the user if SCLOCK idles high.
Cleared by the user if SCLOCK idles low.
2 CPHA
1
Clock Phase Select Bit.
Set by the user if leading SCLOCK edge is to transmit data.
Cleared by the user if trailing SCLOCK edge is to transmit data.
1 SPR1 SPI Bit Rate Select Bits.
0 SPR0 These bits select the SCLOCK rate (bit rate) in master mode as follows:
SPR1 SPR0 Selected Bit Rate
0 0 f
OSC
/2
0 1 f
OSC
/4
1 0 f
OSC
/8
1 1 f
OSC
/16
In SPI slave mode, i.e., SPIM = 0, the logic level on the external SS
pin can be read via the SPR0 bit.
1
The CPOL and CPHA bits should both contain the same values for master and slave devices.
SPIDAT SPI Data Register
Function SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to
read data just received by the SPI interface.
SFR Address F7H
Power-On Default 00H
Bit Addressable No