Datasheet

ADuC841/ADuC842/ADuC843
Rev. 0 | Page 84 of 88
Parameter
SPI SLAVE MODE TIMING (CPHA = 1) Min Typ Max Unit
t
SS
SS
to SCLOCK Edge
0 ns
t
SL
SCLOCK Low Pulse Width 330 ns
t
SH
SCLOCK High Pulse Width 330 ns
t
DAV
Data Output Valid after SCLOCK Edge 50 ns
t
DSU
Data Input Setup Time before SCLOCK Edge 100 ns
t
DHD
Data Input Hold Time after SCLOCK Edge 100 ns
t
DF
Data Output Fall Time 10 25 ns
t
DR
Data Output Rise Time 10 25 ns
t
SR
SCLOCK Rise Time 10 25 ns
t
SF
SCLOCK Fall Time 10 25 ns
t
SFS
SS
High after SCLOCK Edge
0 ns
MISO
MOSI
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
SS
MSB
BITS 6–1
LSB
BITS 6–1
LSB IN
t
DHD
t
DSU
t
DR
t
DF
t
DAV
t
SH
t
SL
t
SR
t
SF
t
SFS
MSB IN
t
SS
03260-0-094
Figure 93. SPI Slave Mode Timing (CPHA = 1)