Datasheet

ADuC836
–66–
ADuC836
–67–
DGNDAGND
PL
ACE ANALOG
CO
MPONENTS
HE
RE
PL
ACE DIGITAL
CO
MPONENTS
HE
RE
GND
PL
ACE ANALOG
CO
MPONENTS
HE
RE
PL
ACE DIGITAL
CO
MPONENTS
HE
RE
DGND
a.
AGND
PLACE ANALOG
CO
MPONENTS
HE
RE
PL
ACE DIGITAL
CO
MPONENTS
HE
RE
b.
c.
Figure 64. System Grounding Schemes
If the user plans to connect fast logic signals (rise/fall time < 5 ns)
to any of the ADuC836’s digital inputs, add a series resistor to
each relevant line to keep rise and fall times longer than 5 ns at the
ADuC836 input pins. A value of 100  or 200  is usually suf-
cient to prevent high speed signals from coupling capacitively into
the ADuC836 and affecting the accuracy of ADC conversions.
ADuC836 System Self-Identication
In some hardware designs, it may be an advantage for the software
running on the ADuC836 target to identify the host MicroCon-
verter. For example, code running on the ADuC836 may also
be used with the ADuC824 or the ADuC816, and is required to
operate differently.
The CHIPID SFR is a read-only register located at SFR address
C2H. The upper nibble of this SFR designates the MicroConverter
within the - ADC family. User software can read this SFR to
identify the host MicroConverter and thus execute slightly differ-
ent code if required. The CHIPID SFR reads as follows for the
- ADC family of MicroConverter products.
ADuC836 CHIPID = 3xH
ADuC834 CHIPID = 2xH
ADuC824 CHIPID = 0xH
ADuC816 CHIPID = 1xH
Clock Oscillator
As described earlier, the core clock frequency for the ADuC836
is generated from an on-chip PLL that locks onto a multiple (384
times) of 32.768 kHz. The latter is generated from an internal
clock oscillator. To use the internal clock oscillator, connect a
32.768 kHz parallel resonant crystal between the XTAL1 and
XTAL2 pins (32 and 33), as shown in Figure 65.
As shown in the typical external crystal connection diagram in
Figure 65, two internal 12 pF capacitors are provided on-chip.
These are connected internally, directly to the XTAL1 and
XTAL2 pins, and the total input capacitances at both pins is
detailed in the Specications table. The value of the total load
capacitance required for the external crystal should be the value
recommended by the crystal manufacturer for use with that
specic crystal. In many cases, because of the on-chip capacitors,
additional external load capacitors will not be required.
XTAL2
XTAL1
32.768kHz
TO INTERNAL
PLL
ADuC836
12pF
12pF
32
33
Figure 65. External Parallel Resonant Crystal
Connections Other Hardware Considerations
To facilitate in-circuit programming plus in-circuit debug and
emulation options, users will want to implement some simple
connection points in their hardware that will allow easy access to
Download, Debug, and Emulation modes.
REV. A
REV. A