Datasheet

ADuC836
–44–
ADuC836
–45–
SPIDAT SPI Data Register
Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read
data just received by the SPI interface.
SFR Address F7H
Power-On Default Value 00H
Bit Addressable No
Depending on the conguration of the bits in the SPICON SFR
shown in Table XXI, the ADuC836 SPI interface will transmit
or receive data in a number of possible modes. Figure 34 shows
all possible ADuC836 SPI congurations and the timing rela-
tionships and synchronization between the signals involved. Also
shown in this gure is the SPI Interrupt bit (ISPI) and how it is
triggered at the end of each byte-wide communication.
SCLOCK
(C
POL = 1)
SCLOCK
(C
POL = 0)
(C
PHA = 1)
(C
PHA = 0)
SAMPLE INPUT
ISPI FLAG
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
?
MSB BIT 6 BIT 5
?
BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS
Figure 34. SPI Timing, All Modes
SPI Interface—Master Mode
In Master mode, the SCLOCK pin is always an output and gen-
erates a burst of eight clocks whenever user code writes to the
SPIDAT Register. The SCLOCK bit rate is determined by SPR0
and SPR1 in SPICON. It should also be noted that the SS pin
is not used in Master mode. If the ADuC836 needs to assert
the SS pin on an external slave device, a port digital output pin
should be used.
In Master mode, a byte transmission or reception is initiated
by a write to SPIDAT. Eight clock periods are generated via
the SCLOCK pin and the SPIDAT byte being transmitted via
MOSI. With each SCLOCK period, a data bit is also sampled
via MISO. After eight clocks, the transmitted byte will have been
completely transmitted and the input byte will be waiting in the
input shift register. The ISPI ag will be set automatically and an
interrupt will occur if enabled. The value in the shift register will
be latched into SPIDAT.
SPI Interface—Slave Mode
In Slave mode, the SCLOCK is an input. The SS pin must also
be driven low externally during the byte communication. Trans-
mission is also initiated by a write to SPIDAT. In Slave mode,
a data bit is transmitted via MISO and a data bit is received via
MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte will have been completely transmitted and
the input byte will be waiting in the input shift register. The ISPI
ag will be set automatically and an interrupt will occur if enabled.
The value in the shift register will be latched into SPIDAT only
when the transmission/reception of a byte has been completed.
The end of transmission occurs after the eighth clock has been
received, if CPHA = 1 or when SS returns high if CPHA = 0.
REV. A
REV. A