Datasheet

ADuC836
–28–
ADuC836
–29–
ADC Chopping
Both ADCs on the ADuC836 implement a chopping scheme
whereby the ADC repeatedly reverses its inputs. The decimated
digital output words from the Sinc
3
lters therefore have a positive
offset and negative offset term included.
As a result, a nal summing stage is included in each ADC so that
each output word from the lter is summed and averaged with
the previous lter output to produce a new valid output result
to be written to the ADC data SFRs. In this way, while the ADC
throughput or update rate is as discussed earlier and illustrated in
Table VIII, the full settling time through the ADC (or the time to
a rst conversion result) will actually be given by 2  t
ADC
.
The chopping scheme incorporated in the ADuC836 ADC results
in excellent dc offset and offset drift specications and is extremely
benecial in applications where drift, noise rejection, and optimum
EMI rejection are important factors.
Calibration
The ADuC836 provides four calibration modes that can be pro-
grammed via the mode bits in the ADCMODE SFR detailed in
Table V. In fact, every ADuC836 has already been factory cali-
brated. The resultant Offset and Gain calibration coefcients
for both the primary and auxiliary ADCs are stored on-chip in
manufacturing-specic Flash/EE memory locations. At power-on
or after reset, these factory calibration coefcients are automati-
cally downloaded to the calibration registers in the ADuC836
SFR space. Each ADC (primary and auxiliary) has dedicated
calibration SFRs, which have been described earlier as part of the
general ADC SFR description. However, the factory calibration
values in the ADC calibration SFRs will be overwritten if any
one of the four calibration options are initiated and that ADC is
enabled via the ADC enable bits in ADCMODE.
Even though an internal offset calibration mode is described
below, it should be recognized that both ADCs are chopped. This
chopping scheme inherently minimizes offset and means that an
internal offset calibration should never be required. Also, because
factory 5 V/25°C gain calibration coefcients are automatically
present at power-on an internal full-scale calibration will only be
required if the part is being operated at 3 V or at temperatures
signicantly different from 25°C.
The ADuC836 offers internal or system calibration facilities. For
full calibration to occur on the selected ADC, the calibration
logic must record the modulator output for two different input
conditions: zero-scale and full-scale points. These points are
derived by performing a conversion on the different input volt-
ages provided to the input of the modulator during calibration.
The result of the zero-scale calibration conversion is stored in the
Offset Calibration Registers for the appropriate ADC. The result
of the full-scale calibration conversion is stored in the Gain Cali-
bration Registers for the appropriate ADC. With these readings,
the calibration logic can calculate the offset and the gain slope for
the input-to-output transfer function of the converter.
During an internal zero-scale or full-scale calibration, the respective
zero-scale input and full-scale inputs are automatically connected to
the ADC input pins internally to the device. A system calibration,
however, expects the system zero-scale and system full-scale volt-
ages to be applied to the external ADC pins before the calibration
mode is initiated. In this way, external ADC errors are taken into
account and minimized as a result of system calibration. It should
also be noted that to optimize calibration accuracy, all ADuC836
ADC calibrations are carried out automatically at the slowest
update rate.
Internally in the ADuC836, the coefcients are normalized before
being used to scale the words coming out of the digital lter. The
offset calibration coefcient is subtracted from the result prior to
the multiplication by the gain coefcient.
From an operational point of view, a calibration should be treated
like another ADC conversion. A zero-scale calibration (if required)
should always be carried out before a full-scale calibration. System
software should monitor the relevant ADC RDY0/1 bit in the
ADCSTAT SFR to determine end of calibration via a polling
sequence or interrupt driven routine.
REV. A
REV. A