Datasheet

ADuC836
–8–
ADuC836
–9–
NOTES
1
Temperature range for ADuC836BS (MQFP package) is –40°C to +125°C. Temperature range for ADuC836BCP (CSP package) is –40°C to +85°C.
2
These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
3
System Zero-Scale Calibration can remove this error.
4
The primary ADC is factory calibrated at 25°C with AV
DD
= DV
DD
= 5 V yielding this full-scale error of 10 V. If user power supply or temperature conditions are signicantly
different from these, an Internal Full-Scale Calibration will restore this error to 10 V. A system zero-scale and full-scale calibration will remove this error altogether.
5
Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.
6
The auxiliary ADC is factory calibrated at 25°C with AV
DD
= DV
DD
= 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration
will remove this error altogether.
7
DAC linearity and ac specications are calculated using: reduced code range of 48 to 4095, 0 to V
REF
; reduced code range of 100 to 3950, 0 to V
DD
.
8
Gain Error is a measurement of the span error of the DAC.
9
In general terms, the bipolar input voltage range to the primary ADC is given by Range
ADC
= ±(V
REF
2
RN
)/125, where:
V
REF
= REFIN(+) to REFIN(–) voltage and V
REF
= 1.25 V when internal ADC V
REF
is selected. RN = decimal equivalent of RN2, RN1, RN0, e.g.,
V
REF
= 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the Range
ADC
= ±1.28 V. In Unipolar mode, the effective range is 0 V to 1.28 V in our example.
10
1.25 V is used as the reference voltage to the auxiliary ADC when internal V
REF
is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively.
11
In Bipolar mode, the auxiliary ADC can only be driven to a minimum of AGND – 30 mV as indicated by the auxiliary ADC absolute AIN voltage limits. The bipolar
range is still –V
REF
to +V
REF
; however, the negative voltage is limited to –30 mV.
12
The ADuC836BCP (CSP package) has been qualied and tested with the base of the CSP package oating.
13
Pins congured in SPI mode, pins congured as digital inputs during this test.
14
Pins congured in I
2
C mode only.
15
Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.
16
Endurance is qualied to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, +85°C, and +125°C. Typical endurance at 25°C is 700 Kcycles.
17
Retention lifetime equivalent at junction temperature (T
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV will
derate with junction temperature as shown in Figure 16 in the Flash/EE Memory section.
18
Power Supply current consumption is measured in Normal, Idle, and Power-Down modes under the following conditions:
Normal mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.
Power-Down mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, all other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON,
PCON.1 = 1, Core Execution suspended in Power-Down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR.
19
DV
DD
power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
Specications subject to change without notice.
REV. A
REV. A