Datasheet

ADuC836
–74–
ADuC836
–75–
Parameter Min Typ Max Unit
SPI MASTER MODE TIMING (CPHA = 1)
t
SL
SCLOCK Low Pulsewidth* 630 ns
t
SH
SCLOCK High Pulsewidth* 630 ns
t
DAV
Data Output Valid after SCLOCK Edge 50 ns
t
DSU
Data Input Setup Time before SCLOCK Edge 100 ns
t
DHD
Data Input Hold Time after SCLOCK Edge 100 ns
t
DF
Data Output Fall Time 10 25 ns
t
DR
Data Output Rise Time 10 25 ns
t
SR
SCLOCK Rise Time 10 25 ns
t
SF
SCLOCK Fall Time 10 25 ns
*Characterized under the following conditions:
Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 1.57 MHz, and SPI bit rate selection bits
SPR1 and SPR0 in SPICON SFR are both set to 0.
SCLOCK
(C
POL = 0)
t
DSU
SCLOCK
(C
POL = 1)
MOSI
MISO
MSB
LSB
LSB IN
BITS 6–1
BITS 6–1
t
DHD
t
DR
t
DAV
t
DF
t
DOSU
t
SH
t
SL
t
SR
t
SF
MSB IN
Figure 75. SPI Master Mode Timing (CPHA = 1)
REV. A
REV. A