Datasheet

ADuC836
–54–
ADuC836
–55–
TIMER/COUNTER 2 OPERATING MODES
The following paragraphs describe the operating modes for
Timer/Counter 2. The operating modes are selected by bits in the
T2CON SFR, as shown in Table XXIX.
Table XXVIII. Timer 2 Operating Modes
RCLK (or) TCLK CAP2 TR2 MODE
0 0 1 16-Bit Autoreload
0 1 1 16-Bit Capture
1 X 1 Baud Rate
X X 0 OFF
16-Bit Autoreload Mode
Autoreload mode has two options, which are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, when Timer 2 rolls over,
it not only sets TF2 but also causes the Timer 2 registers to be
reloaded with the 16-bit value in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = 1, Timer 2 still
performs the above, but with the added feature that a 1-to-0 tran-
sition at external input T2EX will also trigger the 16-bit reload
and set EXF2. The Autoreload mode is illustrated in Figure 52.
16-Bit Capture Mode
Capture Mode has two options, which are selected by bit EXEN2
in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter
that, upon overowing, sets bit TF2, the Timer 2 overow bit,
which can be used to generate an interrupt. If EXEN2 = 1, Timer 2
still performs the above, but a l-to-0 transition on external input
T2EX causes the current value in the Timer 2 registers, TL2
and TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2
in T2CON to be set; EXF2, like TF2, can generate an interrupt.
Capture mode is illustrated in Figure 53.
The baud rate generator mode is selected by RCLK = 1 and/or
TCLK = 1.
In either case, if Timer 2 is being used to generate the baud rate,
the TF2 interrupt ag will not occur. Therefore Timer 2 inter-
rupts will not occur so they do not have to be disabled. However,
in this mode, the EXF2 ag can still cause interrupts and this can
be used as a third external interrupt.
Baud rate generation will be described as part of the UART serial
port operation.
CORE
CLK *
12
T2
PIN
C/ T2 = 0
C/ T2 = 1
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
RELOAD
TF2
EXF2
TIMER
INTERRUP
T
EXEN2
CONTROL
TRANSITION
DETECTOR
T2EX
PIN
RCAP2L RCAP2H
*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 52. Timer/Counter 2, 16-Bit Autoreload Mode
TF2
CORE
CLK *
12
T2
PIN
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
CAPTURE
EXF2
TIMER
INTERRUP
T
EXEN2
CONTROL
TRANSITION
DETECTOR
T2EX
PIN
RCAP2L RCAP2H
C/ T2 = 0
C/ T2 = 1
*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 53. Timer/Counter 2, 16-Bit Capture Mode
REV. A
REV. A