Datasheet

ADuC836
–50–
ADuC836
–51–
Notice also that direct access to the SCLOCK and SDATA/MOSI
pins is afforded through the SFR interface in I
2
C master mode.
Therefore, if you are not using the SPI or I
2
C functions, you can
use these two pins to provide additional high current digital outputs.
HARDWARE SPI
(MASTER/SLAVE)
Q3
SCHMITT
TRIGGER
Q1
Q2 (OFF)
DV
DD
SCLOCK
PIN
Q4 (OFF)
SPE = 1 (SPI ENABLE)
Figure 42. SCLOCK Pin I/O Functional Equivalent
in SPI Mode
MCO
I
2
CM
SFR
BITS
50ns GLITCH
REJECTION FILTER
HARDWARE I
2
C
(SLAVE ONLY)
Q3
Q4
SCLOCK
PIN
Q2
Q1
(OFF)
DV
DD
SPE = 0 (I
2
C ENABLE)
Figure 43. SCLOCK Pin I/O Functional Equivalent
in I
2
C Mode
HARDWARE SPI
(MASTER/SLAVE)
Q3
Q1
Q2 (OFF)
DV
DD
SDATA/
MOSI
PIN
Q4 (OFF)
SPE = 1 (SPI ENABLE)
Figure 44. SDATA/MOSI Pin I/O Functional Equivalent
in SPI Mode
Q3
Q4
Q2
Q1
(OFF)
DV
DD
MDI
MDO
MDE
I2CM
HARDWARE I
2
C
(SLAVE ONLY)
50ns GLITCH
REJECTION FILTER
SDATA/
MOSI
PIN
SFR
BITS
SPE = 0 (I
2
C ENABLE)
Figure 45. SDATA/MOSI Pin I/O Functional Equivalent
in I
2
C Mode
As shown in Figure 46, the MISO pin in SPI master/slave opera-
tion offers the exact same pull-up and pull-down conguration as
the MOSI pin in SPI slave/master operation.
The SS pin has a weak internal pull-up permanently enabled to
prevent the SS input from oating. This pull-up can be easily
overdriven by an external device to drive the SS pin low.
HARDWARE SPI
(MASTER/SLAVE)
MISO
PIN
DV
DD
Figure 46. MISO Pin I/O Functional Equivalent
HARDWARE SPI
(MASTER/SLAVE)
SS
PIN
DV
DD
Figure 47. SS Pin I/O Functional Equivalent
Read-Modify-Write Instructions
Some 8051 instructions that read a port, read the latch and
others read the pin. The instructions that read the latch rather
than the pins are the ones that read a value, possibly change it,
and then rewrite it to the latch. These are called “read-modify-
write” instructions. which are listed below. When the destination
operand is a port or a port bit, these instructions read the latch
rather than the pin.
ANL (Logical AND, e.g., ANL P1, A)
ORL (Logical OR, e.g., ORL P2, A)
XRL (Logical EX-OR, e.g., XRL P3, A)
JBC (Jump If Bit = 1 and Clear Bit,
e.g., JBC P1.1, LABEL
CPL (Complement Bit, e.g., CPL P3.0)
INC (Increment, e.g., INC P2)
DEC (Decrement, e.g., DEC P2)
DJNZ (Decrement and Jump IFf Not Zero,
e.g.,DJNZ P3, LABEL)
MOV PX.Y, C* (Move Carry to Bit Y of Port X)
CLR PX.Y* (Clear Bit Y of Port X)
SETB PX.Y* (Set Bit Y of Port X)
*These instructions read the port byte (all eight bytes), modify the addressed bit
and then write the new byte back to the latch.
The reason that read-modify-write instructions are directed to
the latch rather than to the pin is to avoid a possible misinter-
pretation of the voltage level of a pin. For example, a port pin
might be used to drive the base of a transistor. When a 1 is written
to the bit, the transistor is turned on. If the CPU then reads the
same port bit at the pin rather than the latch, it will read the base
voltage of the transistor and interpret it as a Logic 0. Reading the
latch rather than the pin will return the correct value of 1.
REV. A
REV. A