Datasheet

ADuC836
–42–
ADuC836
–43–
Table XX. PSMCON SFR Bit Designations
Bit Name Description
7 CMPD DV
DD
Comparator Bit.
This is a read-only bit and directly reects the state of the DV
DD
comparator.
Read 1 indicates the DV
DD
supply is above its selected trip point.
Read 0 indicates the DV
DD
supply is below its selected trip point.
6 CMPA AV
DD
Comparator Bit.
This is a read-only bit and directly reects the state of the AVDD comparator.
Read 1 indicates the AV
DD
supply is above its selected trip point.
Read 0 indicates the AV
DD
supply is below its selected trip point.
5 PSMI Power Supply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating low analog or digital
supply. The PSMI Bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain)
high, a 250 ms counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be
written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI.
4 TPD1 DV
DD
Trip Point Selection Bits.
3 TPD0 These bits select the DV
DD
trip point voltage as follows:
TPD1 TPD0 Selected DV
DD
Trip Point (V)
0 0 4.63
0 1 3.08
1 0 2.93
1 1 2.63
2 TPA1 AVDD Trip Point Selection Bits.
1 TPA0 These bits select the AV
DD
trip point voltage as follows:
TPA1 TPA0 Selected AV
DD
Trip Point (V)
0 0 4.63
0 1 3.08
1 0 2.93
1 1 2.63
0 PSMEN Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the Power Supply Monitor Circuit.
Cleared to 0 by the user to disable the Power Supply Monitor Circuit.
POWER SUPPLY MONITOR
As its name suggests, the Power Supply Monitor, once enabled,
monitors both supplies (AV
DD
or DV
DD
) on the ADuC836. It will
indicate when any of the supply pins drops below one of four
user-selectable voltage trip points from 2.63 V to 4.63 V. For cor-
rect operation of the Power Supply Monitor function, AV
DD
must
be equal to or greater than 2.7 V. Monitor function is controlled via
the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor
will interrupt the core using the PSMI bit in the PSMCON SFR.
This bit will not be cleared until the failing power supply has
returned above the trip point for at least 250 ms. This monitor
function allows the user to save working registers to avoid possible
data loss due to the low supply condition, and also ensures that
normal code execution will not resume until a safe supply level
has been well established. The supply monitor is also protected
against spurious glitches triggering the interrupt circuit.
PSMCON Power Supply Monitor Control Register
SFR Address DFH
Power-On Default Value DEH
Bit Addressable No
REV. A
REV. A