Datasheet

ADuC836
–20–
ADuC836
–21–
ADC0H/ADC0M (Primary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the primary ADC.
SFR Address ADC0H High Data Byte DBH
ADC0M Middle Data Byte DAH
Power-On Default Value 00H ADC0H, ADC0M
Bit Addressable No ADC0H, ADC0M
ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC.
SFR Address ADC1H High Data Byte DDH
ADC1L Low Data Byte DCH
Power-On Default Value 00H ADC1H, ADC1L
Bit Addressable No ADC1H, ADC1L
OF0H/OF0M (Primary ADC Offset Calibration Registers*)
These two 8-bit registers hold the 16-bit offset calibration coefcient for the primary ADC. These registers are congured at power-on
with a factory default value of 800000H. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register.
SFR Address OF0H Primary ADC Offset Coefcient High Byte E3H
OF0M Primary ADC Offset Coefcient Middle Byte E2H
Power-On Default Value 80000H OF0H, OF0M respectively
Bit Addressable No OF0H, OF0M
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers*)
These two 8-bit registers hold the 16-bit offset calibration coefcient for the auxiliary ADC. These registers are congured at power-on
with a factory default value of 8000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration
of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register.
SFR Address OF1H Auxiliary ADC Offset Coefcient High Byte E5H
OF1L Auxiliary ADC Offset Coefcient Low Byte E4H
Power-On Default Value 8000H OF1H and OF1L, respectively
Bit Addressable No OF1H, OF1L
GN0H/GN0M (Primary ADC Gain Calibration Registers*)
These two 8-bit registers hold the 16-bit gain calibration coefcient for the primary ADC. These registers are congured at power-on
with a factory-calculated internal full-scale calibration coefcient. Every device will have an individual coefcient. However, these bytes
will be automatically overwritten if an internal or system full-scale calibration of the primary ADC is initiated by the user via MD2–0
bits in the ADCMODE Register.
SFR Address GN0H Primary ADC Gain Coefcient High Byte EBH
GN0M Primary ADC Gain Coefcient Middle Byte EAH
Power-On Default Value Congured at Factory Final Test; See Notes above.
Bit Addressable No GN0H, GN0M
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers*)
These two 8-bit registers hold the 16-bit gain calibration coefcient for the auxiliary ADC. These registers are congured at power-on
with a factory-calculated internal full-scale calibration coefcient. Every device will have an individual coefcient. However, these bytes
will be automatically overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via MD2–0
bits in the ADCMODE Register.
SFR Address GN1H Auxiliary ADC Gain Coefcient High Byte EDH
GN1L Auxiliary ADC Gain Coefcient Low Byte ECH
Power-On Default Value Congured at Factory Final Test; see notes above.
Bit Addressable No GN1H, GN1L
*These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
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