MicroConverter ®, Dual 16-Bit - ADCs with Embedded 62 kB Flash MCU ADuC836 FEATURES High Resolution - ADCs 2 Independent ADCs (16-Bit Resolution) 16-Bit No Missing Codes, Primary ADC 16-Bit rms (16-Bit p-p) Effective Resolution @ 20 Hz Offset Drift 10 nV/C, Gain Drift 0.
ADuC836 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . . .29 Flash/EE Memory and the ADuC836 . . . . . . . . . . . . . . . . .29 ADuC836 Flash/EE Memory Reliability . . . . . . . . . . . . . . .29 Flash/EE Program Memory . . . . . . . . . . . . . . . . . . . . . . . .30 Serial Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPECIFICATIONS1 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN to TMAX, unless otherwise noted.
ADuC836 SPECIFICATIONS (continued) Parameter INTERNAL REFERENCE ADC Reference Reference Voltage Power Supply Rejection Reference Tempco DAC Reference Reference Voltage Power Supply Rejection Reference Tempco ADuC836 Test Conditions/Comments Unit 1.25 ± 1% 45 100 Initial Tolerance @ 25°C, VDD = 5 V V min/max dBs typ ppm/°C typ 2.
ADuC836 Parameter ADuC836 TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current –100 AIN– Current +100 Initial Tolerance @ 25°C Drift ±10 0.
ADuC836 SPECIFICATIONS (continued) Parameter ADuC836 Test Conditions/Comments Unit VDD = 5 V, ISOURCE = 80 A VDD = 3 V, ISOURCE = 20 A ISINK = 8 mA, SCLOCK, MOSI/SDATA ISINK = 10 mA, P1.0 and P1.1 ISINK = 1.6 mA, All Other Outputs V min V min V max V max V max A max pF typ 2.63 4.63 ±3.0 ±4.0 2.63 4.63 ±3.0 ±4.
ADuC836 Parameter POWER REQUIREMENTS Power Supply Voltages AVDD, 3 V Nominal Operation AVDD, 5 V Nominal Operation DVDD, 3 V Nominal Operation DVDD, 5 V Nominal Operation ADuC836 Test Conditions/Comments 2.7 3.6 4.75 5.25 2.7 3.6 4.75 5.
ADuC836 NOTES 1 Temperature range for ADuC836BS (MQFP package) is –40°C to +125°C. Temperature range for ADuC836BCP (CSP package) is –40°C to +85°C. 2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 System Zero-Scale Calibration can remove this error. 4 The primary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of 10 V.
ADuC836 ABSOLUTE MAXIMUM RATINGS1 PIN CONFIGURATIONS 52-Lead MQFP (TA= 25°C, unless otherwise noted.) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND2 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AVDD to DVDD . . . . .
ADuC836 AIN1 BUF AIN MUX AIN2 AIN3 AIN5 TEMP SENSOR PGA BAND GAP REFERENCE REFIN ADC CONTROL AND CALIBRATION 19 MCU CORE DUAL 16-BIT PWM DGND RESET SINGLE-PIN EMULATOR 40 42 26 27 14 13 32 33 XTAL1 DVDD 41 XTAL2 AGND 17 SS AVDD 16 DAC 1 PWM0 2 PWM1 22 T0 23 T1 1 T2 2 T2EX 18 INT0 19 INT1 OSC MISO 15 SPI/I2C SERIAL INTERFACE MOSI/SDATA 47 21 35 WAKE-UP/ RTC TIMER SCLOCK 20 34 48 16-BIT COUNTER TIMERS PLL WITH PROG.
ADuC836 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type* Description P1.4/AIN1 P1.5/AIN2 P1.6/AIN3 P1.7/AIN4/DAC I I I I/O Primary ADC, Positive Analog Input Primary ADC, Negative Analog Input Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The voltage output from the DAC can also be configured to appear at this pin.
ADuC836 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type* Description 40 43 EA I/O External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F7FFh. When held low, this input enables the device to fetch all instructions from external program memory. To determine the mode of code execution, i.e.
ADuC836 MEMORY ORGANIZATION Reset initializes the stack pointer to location 07H. Any call or push pre-increments the SP before loading the stack. Therefore, loading the stack starts from location 08H, which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the stack pointer should be initialized to an area of RAM not used for data storage.
ADuC836 SPECIAL FUNCTION REGISTERS (SFRS) When accessing the internal XRAM, the P0 and P2 port pins, as well as the RD and WR strobes, will not be output as per a standard 8051 MOVX instruction. This allows the user to use these port pins as standard I/O. The upper 1792 bytes of the internal XRAM can be configured to be used as an extended 11-bit stack pointer. By default, the stack will operate exactly like an 8052 in that it will roll over from FFH to 00H in the general-purpose RAM.
ADuC836 Stack Pointer (SP and SPH) Table II. PCON SFR Bit Designations The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the “top of the stack.” The SP Register is incremented before data is stored, during PUSH and CALL executions. While the Stack may reside anywhere in on-chip RAM, the SP Register is initialized to 07H after a reset. This causes the stack to begin at location 08H. As mentioned earlier, the ADuC836 offers an extended 11-bit stack pointer.
ADuC836 COMPLETE SFR MAP not implemented, i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations that are reserved for future use are shaded (RESERVED) and should not be accessed by user software. Figure 6 shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR locations.
ADuC836 ADC SFR INTERFACE Both ADCs are controlled and configured via a number of SFRs that are summarized here and described in more detail in the following sections. ADCSTAT ADC Status Register. Holds general status of the primary and auxiliary ADCs. ADC0M/H Primary ADC 16-bit conversion result is held in these two 8-bit registers. ADCMODE ADC Mode Register.
ADuC836 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable No Table V. ADCMODE SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use 5 ADC0EN Primary ADC Enable. Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0, below. Cleared by the user to place the primary ADC in power-down mode. 4 ADC1EN Auxiliary ADC Enable.
ADuC836 ADC0CON (Primary ADC Control Register) and ADC1CON (Auxiliary ADC Control Register) The ADC0CON and ADC1CON SFRs are used to configure the primary and auxiliary ADC for reference and channel selection, unipolar or bipolar coding and, in the case of the primary ADC, range (the auxiliary ADC operates on a fixed input range of ±VREF).
ADuC836 ADC0H/ADC0M (Primary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the primary ADC. SFR Address Power-On Default Value Bit Addressable ADC0H ADC0M 00H No High Data Byte Middle Data Byte ADC0H, ADC0M ADC0H, ADC0M DBH DAH ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC.
ADuC836 SF (Sinc Filter Register) The number in this register sets the decimation factor and thus the output update rate for the primary and auxiliary ADCs. This SFR cannot be written by user software while either ADC is active. The update rate applies to both primary and auxiliary ADCs and is calculated as follows: f ADC = where: 1 1 × × f MOD 3 8 × SF value for the SF Register is 45H, resulting in a default ADC update rate of just under 20 Hz.
ADuC836 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE via the Sinc Filter (SF) SFR. It is important to note that the peak-to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit. Tables X, XI, and XII show the output rms noise in mV and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates on both the primary and auxiliary ADCs.
ADuC836 PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC836 incorporates two independent - ADCs (primary and auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain gage, pressure transducer, or temperature measurement applications. Primary ADC This ADC is intended to convert the primary sensor input. The input is buffered and can be programmed for one of eight input ranges from ±20 mV to ±2.
ADuC836 Auxiliary ADC The auxiliary ADC is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. This ADC is not buffered and has a fixed input range of 0 V to 2.5 V (assuming an external 2.5 V reference). The single-ended inputs can be driven from AIN3, AIN4, or AIN5 pins, or directly from the on-chip temperature sensor voltage. A block diagram of the auxiliary ADC is shown in Figure 8.
ADuC836 Primary and Auxiliary ADC Inputs 19.372 The output of the Primary ADC multiplexer feeds into a high impedance input stage of the buffer amplifier. As a result, the primary ADC inputs can handle significant source impedances and are tailored for direct connection to external resistive-type sensors like strain gages or Resistance Temperature Detectors (RTDs). ADC INPUT VOLTAGE – mV 19.371 The auxiliary ADC, however, is unbuffered, resulting in higher analog input current on the auxiliary ADC.
ADuC836 Reference Input Excitation Currents The ADuC836’s reference inputs, REFIN(+) and REFIN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AVDD. The nominal reference voltage, VREF (REFIN(+) – REFIN(–)), for specified operation is 2.5 V with the primary and auxiliary reference enable bits set in the respective ADC0CON and/or ADC1CON SFRs. The ADuC836 also contains two identical, 200 µA constant current sources.
ADuC836 Digital Filter 0 The output of the - modulator feeds directly into the digital filter. The digital filter then band-limits the response to a frequency significantly lower than one-half of the modulator frequency. In this manner, the 1-bit output of the comparator is translated into a band-limited, low noise output from the ADuC836 ADCs.
ADuC836 ADC Chopping Both ADCs on the ADuC836 implement a chopping scheme whereby the ADC repeatedly reverses its inputs. The decimated digital output words from the Sinc3 filters therefore have a positive offset and negative offset term included. As a result, a final summing stage is included in each ADC so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the ADC data SFRs.
ADuC836 ADuC836 Flash/EE Memory Reliability NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview The Flash/EE program and data memory arrays on the ADuC836 are fully qualified for two key Flash/EE memory characteristics: Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention. The ADuC836 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit, reprogrammable code and data memory space.
ADuC836 Flash/EE Program Memory (2) Parallel Programming The ADuC836 contains a 64 Kbyte array of Flash/EE program memory. The lower 62 Kbytes of this program memory are available to the user, and can be used for program storage or indeed as additional NV data memory. The Parallel Programming mode is fully compatible with conventional third party Flash or EEPROM device programmers. A block diagram of the external pin configuration required to support parallel programming is shown in Figure 18.
ADuC836 Flash/EE Program Memory Security User Download Mode (ULOAD) In Figure 17 we can see that it was possible to use the 62 Kbytes of Flash/EE program memory available to the user as one single block of memory. In this mode, all of the Flash/EE memory is read only to user code. However, the Flash/EE program memory can also be written to during runtime simply by entering ULOAD mode.
ADuC836 BYTE 2 (0FFDH) BYTE 3 (0FFEH) BYTE 4 (0FFFH) 3FEH BYTE 1 (0FF8H) BYTE 2 (0FF9H) BYTE 3 (0FFAH) BYTE 4 (0FFBH) 03H BYTE 1 (000CH) BYTE 2 (000DH) BYTE 3 (000EH) BYTE 4 (000FH) 02H BYTE 1 (0008H) BYTE 2 (0009H) BYTE 3 (000AH) BYTE 4 (000BH) 01H BYTE 1 (0004H) BYTE 2 (0005H) BYTE 3 (0006H) BYTE 4 (0007H) BYTE 1 (0000H) BYTE 2 (0001H) BYTE 3 (0002H) BYTE 4 (0003H) 00H A block diagram of the SFR interface to the Flash/EE data memory array is shown in Figure 20.
ADuC836 Programming the Flash/EE Data Memory A user wishes to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other three bytes already in this page. A typical program of the Flash/EE Data array will involve: 1. Setting EADRH/L with the page address 2. Writing the data to be programmed to the EDATA1–4 3.
ADuC836 DAC The ADuC836 incorporates a 12-bit voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 k/100 pF. It has two selectable ranges, 0 V to VREF (the internal band gap 2.5 V reference) and 0 V to AVDD. It can operate in 12-bit or 8-bit mode. The DAC has a control register, DACCON, and two data registers, DACH/L. The DAC output can be programmed to appear at Pin 3 or Pin 12.
ADuC836 4 VDD VDD–50mV DAC LOADED WITH 0FFFH OUTPUT VOLTAGE – V VDD–100mV 3 1 100mV DAC LOADED WITH 0000H 50mV 0mV 0 FFFH 000H Figure 22. Endpoint Nonlinearities Due to Amplifier Saturation Note that Figure 22 represents a transfer function in 0-to-VDD mode only. In 0-to-VREF mode (with VREF < VDD), the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the “ideal” line right to the end, showing no signs of endpoint linearity errors.
ADuC836 PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC836 is a highly flexible PWM offering programmable resolution and input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the PWM to be configured as a - DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 26. 12.583MHz PWMCLK CLOCK SELECT 32.768kHz 32.768kHz/15 16-BIT PWM COUNTER Figure 26.
ADuC836 PWM MODES OF OPERATION Mode 0: PWM Disabled PWM1L PWM COUNTER The PWM is disabled, allowing P1.0 and P1.1 to be used as normal. PWM0H Mode 1: Single Variable Resolution PWM PWM0L In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. PWM1H 0 P1.0 PWM1H/L sets the period of the output waveform. Reducing PWM1H/L reduces the resolution of the PWM output but increases the maximum output rate of the PWM (e.g.
ADuC836 Mode 4: Dual NRZ 16-Bit - DAC PWM1L PWM COUNTERS Mode 4 provides a high speed PWM output similar to that of a - DAC. Typically, this mode will be used with the PWM clock equal to 12.58 MHz. PWM1H PWM0L In this mode, P1.0 and P1.1 are updated every PWM clock (80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit PWM), PWM0 (P1.0) is high for PWM0H/L cycles and low for (65536 – PWM0H/L) cycles. Similarly, PWM1 (P1.1) is high for PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.
ADuC836 ON-CHIP PLL The ADuC836 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, to allow power saving in cases where maximum core performance is not PLLCON PLL Control Register SFR Address Power-On Default Value Bit Addressable D7H 03H No required. The default core clock is the PLL clock divided by 8 or 1.572864 MHz.
ADuC836 TIME INTERVAL COUNTER (WAKE-UP/RTC TIMER) If the ADuC836 is in Power-Down mode, again with TIC interrupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053H. The TIC-related SFRs are described in Table XVIII with a block diagram of the TIC shown in Figure 33.
ADuC836 INTVAL User Time Interval Select Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. (See IEIP2 SFR description under the Interrupt System section.
ADuC836 WATCHDOG TIMER amount of time (see PRE3–0 bits in WDCON). The watchdog timer itself is a 16-bit counter that is clocked at 32.768 kHz. The watchdog timeout interval can be adjusted via the PRE3–0 bits in WDCON. Full control and status of the watchdog timer function can be controlled via the Watchdog Timer Control SFR (WDCON). The WDCON SFR can only be written by user software if the double write sequence described in WDWR below is initiated on every write access to the WDCON SFR.
ADuC836 POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD or DVDD) on the ADuC836. It will indicate when any of the supply pins drops below one of four user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the Power Supply Monitor function, AVDD must be equal to or greater than 2.7 V. Monitor function is controlled via the PSMCON SFR.
ADuC836 SERIAL PERIPHERAL INTERFACE MISO (Master In, Slave Out Data I/O Pin), Pin 14 The ADuC836 integrates a complete hardware Serial Peripheral Interface (SPI) interface on-chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., fullduplex. It should be noted that the SPI pins SCLOCK and MOSI are multiplexed with the I2C pins SCLOCK and SDATA.
ADuC836 SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. F7H 00H No SFR Address Power-On Default Value Bit Addressable Depending on the configuration of the bits in the SPICON SFR shown in Table XXI, the ADuC836 SPI interface will transmit or receive data in a number of possible modes.
ADuC836 I2C SERIAL INTERFACE The ADuC836 supports a fully licensed* I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA (Pin 27) is the data I/O pin and SCLOCK (Pin 26) is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. Therefore I2CCON SFR Address Power-On Default Value Bit Addressable the user can enable only one interface or the other at any given time (see SPE in Table XXI).
ADuC836 The main features of the MicroConverter I2C interface are: Once enabled in I2C Slave mode, the slave controller waits for a START condition. If the ADuC836 detects a valid start condition followed by a valid address, and by the R/W bit, the I2CI interrupt bit will be automatically set by hardware. Only two bus lines are required: a serial data line (SDATA) and a serial clock line (SCLOCK). An I2C master can communicate with multiple slave devices.
ADuC836 DUAL DATA POINTER DPCON Data Pointer Control SFR The ADuC836 incorporates both main and shadow data pointers. The shadow data pointer is selected via the data pointer control SFR (DPCON). DPCON also includes features such as automatic hardware post-increment and post-decrement, as well as automatic data pointer toggle. DPCON is described in Table XXIII. SFR Address Power-On Default Value Bit Addressable A7H 00H No Table XXIII.
ADuC836 8052 COMPATIBLE ON-CHIP PERIPHERALS Port 1 This section gives a brief overview of the various secondary peripheral circuits, which are also available to the user on-chip. These remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 SFR bit definitions. Port 1 is also an 8-bit port directly controlled via the P1 SFR. The Port 1 pins are divided into two distinct pin groupings: P1.0 to P1.1 and P1.2 to P1.7. P1.0 and P1.1 P1.0 and P1.
ADuC836 P1.2 to P1.7 Port 3 pins also have various secondary functions described in Table XXV. The alternate functions of Port 3 pins can be activated only if the corresponding bit latch in the P3 SFR contains a 1. Otherwise, the port pin is stuck at 0. The remaining Port 1 pins (P1.2 to P1.7) can only be configured as analog input (ADC) or digital input pins. By (power-on) default, these pins are configured as analog inputs, i.e., 1 written in the corresponding Port 1 register bit.
ADuC836 Notice also that direct access to the SCLOCK and SDATA/MOSI pins is afforded through the SFR interface in I2C master mode. Therefore, if you are not using the SPI or I2C functions, you can use these two pins to provide additional high current digital outputs. DVDD SPE = 1 (SPI ENABLE) Q1 As shown in Figure 46, the MISO pin in SPI master/slave operation offers the exact same pull-up and pull-down configuration as the MOSI pin in SPI slave/master operation.
ADuC836 TIMERS/COUNTERS The ADuC836 has three 16-bit Timer/Counters: Timer 0, Timer 1, and Timer 2. The Timer/Counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each Timer/Counter consists of two 8-bit registers: THx and TLx (x = 0, 1, and 2). All three can be configured to operate either as timers or event counters. In Timer function, the TLx Register is incremented every machine cycle.
ADuC836 TCON Timer/Counter 0 and 1 Control Register SFR Address Power-On Default Value Bit Addressable 88H 00H Yes Table XXVII. TCON SFR Bit Designations Bit Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine. 6 TR1 Timer 1 Run Control Bit. Set by user to turn on Timer/Counter 1. Cleared by user to turn off Timer/Counter 1. 5 TF0 Timer 0 Overflow Flag.
ADuC836 TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Auto Reload) The following paragraphs describe the operating modes for Timer/ Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for both Timer 0 and 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 50. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which are preset by software.
ADuC836 TIMER/COUNTER 2 OPERATING MODES 16-Bit Capture Mode The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR, as shown in Table XXIX. Capture Mode has two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt.
ADuC836 T2CON Timer/Counter 2 Control Register SFR Address Power-On Default Value Bit Addressable C8H 00H Yes Table XXIX. T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software. 6 EXF2 Timer 2 External Flag. Set by hardware when either a capture or a reload is caused by a negative transition in T2EX and EXEN2 = 1. Cleared by user software.
ADuC836 SBUF UART SERIAL INTERFACE The serial port is full-duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. The physical interface to the serial data network is via pins RxD(P3.0) and TxD(P3.
ADuC836 Mode 1: 8-Bit UART, Variable Baud Rate To transmit, the eight data bits must be written into SBUF. The ninth bit must be written to TB8 in SCON. When transmission is initiated, the eight data bits (from SBUF) are loaded onto the transmit shift register (LSB first). The contents of TB8 are loaded into the ninth bit position of the transmit shift register. Mode 1 is selected by clearing SM0 and setting SM1. Each data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1).
ADuC836 BAUD RATE GENERATION USING TIMER 1 AND TIMER 2 Timer 1 Generated Baud Rates Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 has a 16-bit Autoreload mode, a wider range of baud rates is possible.
ADuC836 BAUD RATE GENERATION USING TIMER 3 The high integer dividers in a UART block means that high speed baud rates are not always possible using some particular crystals, e.g., using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem, the ADuC836 has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates.
ADuC836 INTERRUPT SYSTEM The ADuC836 provides a total of 11 interrupt sources with two priority levels. The control and configuration of the interrupt system are carried out through three interrupt-related SFRs: the IE (Interrupt Enable) Register, IP (Interrupt Priority Register), and IEIP2 (Secondary Interrupt Enable/Priority SFR) Registers. Their bit definitions are given in the Tables XXXV to XXXVII.
ADuC836 Interrupt Priority Interrupt Vectors The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first.
ADuC836 ADuC836 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC836 into any hardware system. External Memory Interface In addition to its internal program and data memories, the ADuC836 can access up to 64 Kbytes of external program memory (ROM, PROM, and so on) and up to 16 Mbytes of external data memory (SRAM).
ADuC836 Power Supplies The ADuC836’s operational power supply voltage range is 2.7 V to 5.25 V. Although the guaranteed data sheet specifications are given only for power supplies within 2.7 V to 3.6 V or +5% of the nominal 5 V level, the chip will function equally well at any power supply level between 2.7 V and 5.25 V. Separate analog and digital power supply pins (AVDD and DVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals that are often present on the system DVDD line.
ADuC836 Power Saving Modes Wake-Up from Power-Down Latency Setting the Idle and Power-Down Mode Bits, PCON.0 and PCON.1, respectively, in the PCON SFR described in Table II allows the chip to be switched from Normal mode into Idle mode, and also into full Power-Down mode. Even with the 32 kHz crystal enabled during power-down, the PLL will take some time to lock after a wake-up from power-down. Typically, the PLL will take about 1 ms to lock.
ADuC836 a. PLACE DIGITAL COMPONENTS HERE PLACE ANALOG COMPONENTS HERE AGND DGND The CHIPID SFR is a read-only register located at SFR address C2H. The upper nibble of this SFR designates the MicroConverter within the - ADC family. User software can read this SFR to identify the host MicroConverter and thus execute slightly different code if required. The CHIPID SFR reads as follows for the - ADC family of MicroConverter products. ADuC836 ADuC834 ADuC824 ADuC816 b.
ADuC836 OTHER HARDWARE CONSIDERATIONS In-Circuit Serial Download Access Nearly all ADuC836 designs will want to take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the ADuC836’s UART, which requires an external RS-232 chip for level translation if downloading code from a PC. Basic configuration of an RS-232 connection is illustrated in Figure 66 with a simple ADM3202 based circuit.
ADuC836 Typical System Configuration its resistance. This differential voltage is routed directly to the positive and negative inputs of the primary ADC (AIN1, AIN2, respectively). The same current that excited the RTD also flows through a series resistance RREF, generating a ratiometric voltage reference VREF.
ADuC836 QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC836.
ADuC836 TIMING SPECIFICATIONS1, 2, 3 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted.) Parameter 32.768 kHz External Crystal Typ Max Min CLOCK INPUT (External Clock Driven XTAL1) tCK XTAL1 Period tCKL XTAL1 Width Low tCKH XTAL1 Width High tCKR XTAL1 Rise Time tCKF XTAL1 Fall Time 1/tCORE ADuC836 Core Clock Frequency4 tCORE ADuC836 Core Clock Period5 tCYC ADuC836 Machine Cycle Time6 30.52 6.26 6.26 9 9 0.
ADuC836 Parameter EXTERNAL PROGRAM MEMORY tLHLL ALE Pulsewidth tAVLL Address Valid to ALE Low tLLAX Address Hold after ALE Low tLLIV ALE Low to Valid Instruction In tLLPL ALE Low to PSEN Low tPLPH PSEN Pulsewidth tPLIV PSEN Low to Valid Instruction In tPXIX Input Instruction Hold after PSEN tPXIZ Input Instruction Float after PSEN tAVIV Address to Valid Instruction In tPLAZ PSEN Low to Address Float tPHAX Address Hold after PSEN High 12.
ADuC836 Parameter EXTERNAL DATA MEMORY READ CYCLE tRLRH RD Pulsewidth tAVLL Address Valid after ALE Low tLLAX Address Hold after ALE Low tRLDV RD Low to Valid Data In tRHDX Data and Address Hold after RD tRHDZ Data Float after RD tLLDV ALE Low to Valid Data In tAVDV Address to Valid Data In tLLWL ALE Low to RD Low tAVWL Address Valid to RD Low tRLAZ RD Low to Address Float tWHLH RD High to ALE High 12.
ADuC836 Parameter 12.
ADuC836 Parameter 12.58 MHz Core_Clk Min Typ Max UART TIMING (Shift Register Mode) tXLXL Serial Port Clock Cycle Time tQVXH Output Data Setup to Clock tDVXH Input Data Setup to Clock tXHDX Input Data Hold after Clock tXHQX Output Data Hold after Clock 662 292 0 42 0.
ADuC836 Parameter Min SPI MASTER MODE TIMING (CPHA = 1) tSL SCLOCK Low Pulsewidth* tSH SCLOCK High Pulsewidth* tDAV Data Output Valid after SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time Typ Max 630 630 100 100 50 10 10 10 10 25 25 25 25 Unit ns ns ns ns ns ns ns ns ns *Characterized under the following conditions: Core clock divider bits CD2, CD1, an
ADuC836 Parameter Min SPI MASTER MODE TIMING (CPHA = 0) tSL SCLOCK Low Pulsewidth* tSH SCLOCK High Pulsewidth* tDAV Data Output Valid after SCLOCK Edge tDOSU Data Output Setup before SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time Typ Max 630 630 100 100 50 150 10 10 10 10 25 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns *Characterized under the followin
ADuC836 Parameter Min SPI SLAVE MODE TIMING (CPHA = 1) tSS SS to SCLOCK Edge tSL SCLOCK Low Pulsewidth tSH SCLOCK High Pulsewidth tDAV Data Output Valid after SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time tSFS SS High after SCLOCK Edge Typ 0 Max 330 330 100 100 ns ns ns ns ns ns ns ns ns ns ns 50 10 10 10 10 0 Unit 25 25 25 25 SS tSFS tSS SCLOC
ADuC836 Parameter Min SPI SLAVE MODE TIMING (CPHA = 0) tSS SS to SCLOCK Edge tSL SCLOCK Low Pulsewidth tSH SCLOCK High Pulsewidth tDAV Data Output Valid after SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time tSSR SS to SCLOCK Edge tDOSS Data Output Valid after SS Edge tSFS SS High after SCLOCK Edge 0 100 100 Typ Max 330 330 Unit ns ns ns ns ns ns ns ns ns
ADuC836 Parameter Min Max Unit 2 I C-SERIAL INTERFACE TIMING tL SCLOCK Low Pulsewidth tH SCLOCK High Pulsewidth tSHD Start Condition Hold Time tDSU Data Setup Time tDHD Data Hold Time tRSU Setup Time for Repeated Start tPSU Stop Condition Setup Time tBUF Bus Free Time between a STOP Condition and a START Condition tR Rise Time of Both SCLOCK and SDATA tF Fall Time of Both SCLOCK and SDATA tSUP* Pulsewidth of Spike Suppressed 4.7 4.0 0.6 100 µs µs µs ns µs µs µs µs 0.9 0.6 0.6 1.
ADuC836 OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52) Dimensions shown in millimeters 14.15 13.90 SQ 13.65 2.45 MAX 39 27 40 SEATING PLANE C02991–0–4/03(A) 1.03 0.88 0.73 26 7.80 REF 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) VIEW A PIN 1 52 14 1 0.23 0.11 13 0.65 BSC 0.38 0.22 2.10 2.00 1.95 7 0 0.
