Datasheet

REV. A
ADuC834
–79–
Parameter Min Max Unit Figure
I
2
C-SERIAL INTERFACE TIMING
t
L
SCLOCK Low Pulsewidth 4.7 µs79
t
H
SCLOCK High Pulsewidth 4.0 µs79
t
SHD
Start Condition Hold Time 0.6 µs79
t
DSU
Data Setup Time 100 ns 79
t
DHD
Data Hold Time 0.9 µs79
t
RSU
Setup Time for Repeated Start 0.6 µs79
t
PSU
Stop Condition Setup Time 0.6 µs79
t
BUF
Bus Free Time between a STOP 1.3 µs79
Condition and a START Condition
t
R
Rise Time of Both SCLOCK and SDATA 300 ns 79
t
F
Fall Time of Both SCLOCK and SDATA 300 ns 79
t
SUP*
Pulsewidth of Spike Suppressed 50 ns 79
*Input filtering on both the SCLOCK and SDATA inputs surpresses noise spikes less than 50 ns.
MSB
t
BUF
SDATA (I/O)
SCLK (I)
STOP
CONDITION
START
CONDITION
REPEATED
START
LSB ACK MSB
12-78 9 1
S(R)
PS
t
PSU
t
DSU
t
SHD
t
DHD
t
SUP
t
DSU
t
DHD
t
H
t
SUP
t
L
t
RSU
t
R
t
R
t
F
t
F
Figure 79. I
2
C Compatible Interface Timing