Datasheet

REV. A–74–
ADuC834
12.58 MHz Core_Clk Variable Core_Clk
Parameter Min Typ Max Min Typ Max Unit Figure
UART TIMING (Shift Register Mode)
t
XLXL
Serial Port Clock Cycle Time 0.95 12t
CORE
s74
t
QVXH
Output Data Setup to Clock 662 10t
CORE
– 133 ns 74
t
DVXH
Input Data Setup to Clock 292 2t
CORE
+ 133 ns 74
t
XHDX
Input Data Hold after Clock 0 0 ns 74
t
XHQX
Output Data Hold after Clock 42 2t
CORE
– 117 ns 74
SET RI
OR
SET TI
01
BIT 1
t
XLXL
ALE (O)
TxD
(OUTPUT CLOCK)
RxD
(OUTPUT DATA)
RxD
(INPUT DATA)
67
BIT 6
MSB
MSB
BIT 6
BIT 1 LSB
t
XHQX
t
QVXH
t
DVXH
t
XHDX
Figure 74. UART Timing in Shift Register Mode