Datasheet

REV. A
ADuC834
–73–
12.58 MHz Core_Clk Variable Core_Clk
Parameter Min Max Min Max Unit Figure
EXTERNAL DATA MEMORY WRITE CYCLE
t
WLWH
WR Pulsewidth 377 6t
CORE
– 100 ns 73
t
AVLL
Address Valid after ALE Low 39 t
CORE
– 40 ns 73
t
LLAX
Address Hold after ALE Low 44 t
CORE
– 35 ns 73
t
LLWL
ALE Low to WR Low 188 288 3t
CORE
– 50 3t
CORE
+ 50 ns 73
t
AVWL
Address Valid to WR Low 188 4t
CORE
– 130 ns 73
t
QVWX
Data Valid to WR Transition 29 t
CORE
– 50 ns 73
t
QVWH
Data Setup before WR 406 7t
CORE
– 150 ns 73
t
WHQX
Data and Address Hold after WR 29 t
CORE
– 50 ns 73
t
WHLH
WR High to ALE High 39 119 t
CORE
– 40 t
CORE
+ 40 ns 73
t
LLAX
A0–A7
CORE_CLK
ALE (O)
PSEN (O)
PORT 0 (O)
PORT 2 (O)
WR (O)
t
WHLH
t
WHQX
t
WLWH
t
QVWX
t
QVWH
t
LLWL
t
AVWL
t
AVLL
A16–A23
A8–A15
DATA
Figure 73. External Data Memory Write Cycle