Datasheet

REV. A–72–
ADuC834
12.58 MHz Core_Clk Variable Core_Clk
Parameter Min Max Min Max Unit Figure
EXTERNAL DATA MEMORY READ CYCLE
t
RLRH
RD Pulsewidth 377 6t
CORE
– 100 ns 72
t
AVLL
Address Valid after ALE Low 39 t
CORE
– 40 ns 72
t
LLAX
Address Hold after ALE Low 44 t
CORE
– 35 ns 72
t
RLDV
RD Low to Valid Data In 232 5t
CORE
– 165 ns 72
t
RHDX
Data and Address Hold after RD 00 ns72
t
RHDZ
Data Float after RD 89 2t
CORE
– 70 ns 72
t
LLDV
ALE Low to Valid Data In 486 8t
CORE
– 150 ns 72
t
AVDV
Address to Valid Data In 550 9t
CORE
– 165 ns 72
t
LLWL
ALE Low to RD Low 188 288 3t
CORE
– 50 3t
CORE
+ 50 ns 72
t
AVWL
Address Valid to RD Low 188 4t
CORE
– 130 ns 72
t
RLAZ
RD Low to Address Float 0 0 ns 72
t
WHLH
RD High to ALE High 39 119 t
CORE
– 40 t
CORE
+ 40 ns 72
t
LLAX
DATA (IN)
CORE_CLK
ALE (O)
PSEN (O)
PORT 0 (I/O)
PORT 2 (O)
RD (O)
t
LLDV
t
LLWL
t
AVWL
t
AVLL
t
AVDV
t
RLAZ
t
RLDV
t
RHDX
t
RHDZ
t
WHLH
A0–A7
(OUT)
A16–A23
A8–A15
t
RLRH
Figure 72. External Data Memory Read Cycle