Datasheet

REV. A
ADuC834
–71–
12.58 MHz Core_Clk Variable Core_Clk
Parameter Min Max Min Max Unit Figure
EXTERNAL PROGRAM MEMORY
t
LHLL
ALE Pulsewidth 119 2t
CORE
– 40 ns 71
t
AVLL
Address Valid to ALE Low 39 t
CORE
– 40 ns 71
t
LLAX
Address Hold after ALE Low 49 t
CORE
– 30 ns 71
t
LLIV
ALE Low to Valid Instruction In 218 4t
CORE
– 100 ns 71
t
LLPL
ALE Low to PSEN Low 49 t
CORE
– 30 ns 71
t
PLPH
PSEN Pulsewidth 193 3t
CORE
– 45 ns 71
t
PLIV
PSEN Low to Valid Instruction In 133 3t
CORE
– 105 ns 71
t
PXIX
Input Instruction Hold after PSEN 00 ns71
t
PXIZ
Input Instruction Float after PSEN 54 t
CORE
– 25 ns 71
t
AVIV
Address to Valid Instruction In 292 5t
CORE
– 105 ns 71
t
PLAZ
PSEN Low to Address Float 25 25 ns 71
t
PHAX
Address Hold after PSEN High 0 0 ns 71
t
LHLL
t
AVLL
PCL
(OUT)
INSTRUCTION
(IN)
PCH
CORE_CLK
ALE (O)
PSEN (O)
PORT 0 (I/O)
PORT 2 (O)
t
LLPL
t
LLAX
t
PLAZ
t
PXIX
t
PXIZ
t
PLIV
t
LLIV
t
PLPH
t
PHAX
t
AVIV
Figure 71. External Program Memory Read Cycle