Datasheet

REV. A
ADuC834
–57–
UART SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and
receive simultaneously. It is also receive-buffered, meaning it
can commence reception of a second byte before a previously
received byte has been read from the receive register. However,
if the first byte still has not been read by the time reception of
the second byte is complete, the first byte will be lost. The
physical interface to the serial data network is via Pins
RxD(P3.0) and TxD(P3.1), while the SFR interface to the UART
comprises the following registers:
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99H). Writing to SBUF
loads the transmit register and reading SBUF accesses a physically
separate receive register.
SCON UART Serial Port Control Registers
SFR Address 98H
Power-On Default Value 00H
Bit Addressable Yes
Table XXX. SCON SFR Bit Designations
Bit Name Description
7 SM0 UART Serial Mode Select Bits.
6 SM1 These bits select the Serial Port operating mode as follows:
SM0 SM1 Selected Operating Mode
00Mode 0: Shift Register, fixed baud rate (f
CORE
/12)
01Mode 1: 8-bit UART, variable baud rate
10Mode 2: 9-bit UART, fixed baud rate (f
CORE
/64) or (f
CORE
/32)
11Mode 3: 9-bit UART, variable baud rate
5 SM2 Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared. In
Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is cleared,
RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is set, RI will not be
activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte
of data has been received.
4 REN Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
3TB8 Serial Port Transmit (Bit 9).
The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.
2 RB8 Serial Port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.
1TI Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in
Modes 1, 2, and 3.
TI must be cleared by user software.
0RI Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in
Modes 1, 2, and 3.
RI must be cleared by software.
UART OPERATING MODES
Mode 0: 8-Bit Shift Register Mode
Mode 0 is selected by clearing both the SM0 and SM1 bits in the
SFR SCON. Serial data enters and exits through RxD. TxD outputs
the shift clock. Eight data bits are transmitted or received. Trans-
mission is initiated by any instruction that writes to SBUF. The
data is shifted out of the RxD line. The 8 bits are transmitted
with the least-significant bit (LSB) first, as shown in Figure 54.
Reception is initiated when the Receive Enable bit (REN) is
1 and the Receive Interrupt bit (RI) is 0. When RI is cleared,
the data is clocked into the RxD line and the clock pulses are
output from the TxD line.
CORE
CLK
ALE
RxD
(DATA OUT)
TxD
(SHIFT CLOCK)
DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7
S6S5S4S3S2S1S6S5S4S4S3S2S1S6S5S4S3S2S1
MACHINE
CYCLE 8
MACHINE
CYCLE 7
MACHINE
CYCLE 2
MACHINE
CYCLE 1
Figure 54. UART Serial Port Transmission, Mode 0