Datasheet

REV. A–48–
ADuC834
Table XXIII. DPCON SFR Bit Designations
Bit Name Description
7 ––– Reserved for Future Use
6 DPT Data Pointer Automatic Toggle Enable.
Cleared by user to disable auto swapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.
5DP1m1 Shadow Data Pointer Mode
4DP1m0 These two bits enable extra modes of the shadow data pointer operation allowing for more compact
and more efficient code size and execution.
m1 m0 Behavior of the Shadow Data Pointer
008052 Behavior
01DPTR is post-incremented after a MOVX or a MOVC instruction
10DPTR is post-decremented after a MOVX or MOVC instruction
11DPTR LSB is toggled after a MOVX or MOVC instruction
(This instruction can be useful for moving 8-bit blocks to/from 16-bit devices)
3DP0m1 Main Data Pointer Mode
2DP0m0 These two bits enable extra modes of the main data pointer operation allowing for more compact and
more efficient code size and execution.
m1 m0 Behavior of the Main Data Pointer
008052 Behavior
01DPTR is post-incremented after a MOVX or a MOVC instruction
10DPTR is post-decremented after a MOVX or MOVC instruction
11DPTR LSB is toggled after a MOVX or MOVC instruction
(This instruction can be useful for moving 8-bit blocks to/from 16-bit devices)
1 ––– This bit is not implemented to allow the INC DPCON instruction toggle the data pointer without
incrementing the rest of the SFR.
0 DPSEL Data Pointer Select.
Cleared by user to select the main data pointer. This means that the contents of the main 24-bit DPTR
appears in the 3 SFRs DPL, DPH, and DPP.
Set by the user to select the shadow data pointer. This means that the contents of the shadow 24-bit
DPTR appears in the 3 SFRs DPL, DPH, and DPP.
NOTES
1. This is the only place where the main and shadow data pointers are distinguished. Everywhere else in this data sheet, wherever the DPTR is mentioned, operation
on the active DPTR is implied.
2. Only MOVC/MOVX @DPTR instructions are relevant above. MOVC/MOVX PC/@Ri instructions will not cause the DPTR to automatically post increment/decrement,
and so on. To illustrate the operation of DPCON, the following code will copy 256 bytes of code memory at Address D000h into XRAM starting from Address 0000h.
the code uses 16 bytes and 2054 cycles. To perform this on a standard 8051 requires approximately 33 bytes and 7172 cycles (depending on how it is implemented).
DUAL DATA POINTER
The ADuC834 incorporates two data pointers. The second data
pointer is a shadow data pointer and is selected via the data
pointer control SFR (DPCON). DPCON also includes features
such as automatic hardware post-increment and post-decrement,
as well as automatic data pointer toggle. DPCON is described
in Table XXIII.
DPCON Data Pointer Control SFR
SFR Address A7H
Power-On Default Value 00H
Bit Addressable No
MOV DPTR,#0 ; Main DPTR = 0
MOV DPCON,#55h ; Select shadow DPTR
; DPTR1 increment mode,
; DPTR0 increment mode
; DPTR auto toggling ON
MOV DPTR,#0D000h ; Shadow DPTR = D000h
MOVELOOP:
CLR A
MOVC A,@A+DPTR ; Get data
; Post Inc DPTR
; Swap to Main DPTR (Data)
MOVX @DPTR,A ; Put ACC in XRAM
; Increment main DPTR
; Swap to Shad DPTR (Code)
MOV A, DPL
JNZ MOVELOOP