Datasheet
REV. A–42–
ADuC834
Table XIX. WDCON SFR Bit Designations
Bit Name Description
7 PRE3 Watchdog Timer Prescale Bits.
6 PRE2 The Watchdog timeout period is given by the equation: t
WD
= (2
PRE
(2
9
/f
PLL
))
5 PRE1 (0 ≤ PRE ≤ 7; f
PLL
= 32.768 kHz)
4 PRE0 PRE3 PRE2 PRE1 PRE0 Timeout Period (ms) Action
0000 15.6 Reset or Interrupt
0001 31.2 Reset or Interrupt
0010 62.5 Reset or Interrupt
0011 125 Reset or Interrupt
0100 250 Reset or Interrupt
0101 500 Reset or Interrupt
0110 1000 Reset or Interrupt
0111 2000 Reset or Interrupt
1000 0.0 Immediate Reset
PRE3–0 > 1001 Reserved
3 WDIR Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will gener
ate an
interrupt response instead of a system reset when the watchdog timeout period has
expired. This
interrupt is not disabled by the CLR EA
instruction and it is also a fixed, high-prior
ity interrupt. If the
watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler
is used to set the timeout period in which an interrupt will be generated.
(See also Note 1, Table XXXIX in the Interrupt System section.)
2 WDS Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
1 WDE Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters. If a 1 is not written to this bit within the
watchdog timeout period, the watchdog will generate a reset or interrupt, depending on WDIR.
Cleared under the following conditions, User writes 0, Watchdog Reset (WDIR = 0);
Hardware Reset; PSM Interrupt.
0 WDWR Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must
be set and the very next instruction must be a write instruction to the WDCON SFR. For example:
CLR EA ; disable interrupts while writing
; to WDT
SETB WDWR ; allow write to WDCON
MOV WDCON, #72h ; enable WDT for 2.0s timeout
SETB EA ; enable interrupts again (if rqd)
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset or
interrupt within a reasonable amount of time if the ADuC834
enters an erroneous state, possibly due to a programming error,
electrical noise, or RFI. The watchdog function can be disabled
by clearing the WDE (Watchdog Enable) bit in the Watchdog
Control (WDCON) SFR. When enabled; the watchdog circuit
will generate a system reset or interrupt (WDS) if the user program
fails to set the Watchdog (WDE) bit within a predetermined
amount of time (see PRE3–0 bits in WDCON). The watchdog
timer itself is a 16-bit counter that is clocked at 32.768 kHz. The
watchdog timeout interval can be adjusted via the PRE3–0 bits
in WDCON. Full control and status of the watchdog timer
function can be controlled via the Watchdog Timer Control SFR
(WDCON). The WDCON SFR can only be written by user
software if the double write sequence described in WDWR
below is initiated on every write access to the WDCON SFR.
WDCON Watchdog Timer Control Register
SFR Address C0H
Power-On Default Value 10H
Bit Addressable Yes